IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 88

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

IDT IDT88K8483
A (TM)
B (TM)
A (MT)
B (MT)
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
B: 0x2000
A: 0x0000
B: 0x2000
A: 0x0000
B: 0x2000
Address
Module
Base
TM_PFP_REG
MT_PFP_REG
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
AUXILIARY
PRGD
PRGD
PRGD
PRGD
PRGD
PRGD
PRGD
PRGD
PRGD
PMON_EVENT
PMON_EVENT
Block Base
Name
TM - 0x1700
MT - 0x1F00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0A00
0x0B00
0x0B00
0x0B00
0x0B00
0x0B00
0x0B00
0x0B00
0x0B00
0x0B00
0x0F00
0x0F00
Address
Block
Base
Table 18 Indirect Registers Map (Part 7 of 8)
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x07
0x08
0x0E
0x0F
0x12
0x13
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x00
0x01
Register
Offset
TM
A: 0170E
B: 0370E
MT
A: 01F0E
B: 03F0E
B: 02A00
B: 02A01
B: 02A02
B: 02A03
B: 02A04
B: 02A05
B: 02A07
B: 02A08
B: 02A0E
B: 02A0F
B: 02A12
B: 02A13
A: 00B00
A: 00B01
A: 00B02
A: 00B03
B: 02B03
A: 00B04
B: 02B04
A: 00B05
B: 02B05
A: 00B06
B: 02B06
A: 00B07
B: 02B07
A: 00B08
B: 02B08
A: 00F00
B: 02F00
A: 00F01
B: 02F01
88 of 162
Register
Address
Indirect
0x
PFP Maximum Packet Length Register (p. 128)
Auxiliary Interface Enable Register (p. 129)
Auxiliary Interface Configuration Register (p. 129)
Auxiliary Extension Buffer Configuration Register (p. 129)
Auxiliary Clock Monitor Status Register) (p. 130)
External Memory Test Control Register (p. 130)
External Memory Test Results Register (p. 131)
Auxiliary Early Backpressure Threshold Register (p. 131)
Auxiliary Packet Mode Configuration Register (p. 131)
HSTL Test Register (p. 131)
Auxiliary Automatic Impedance Matching Control Register
(p. 132)
Auxiliary Synchronization Status Register (p. 132)
Enable Control Register (p. 133)
Feedback Configuration Register (p. 133)
Bandwidth Control Register (p. 133)
Packet Length Register (p. 134)
Burst Size Register (p. 134)
Random Control Register (p. 134)
LID Register (p. 135)
Synchronization Register (p. 135)
Bit Error Insertion Register (p. 135)
PMON Event Interrupt Indication Register (p. 136)
PMON Event Interrupt Enable Register (p. 139)
Auxiliary Initialization Control Register (p. 133)
Register Description
October 20, 2006