IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 105

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 Registers
SPI-4 Ingress LP to LID Mapping Table
SPI-4 Ingress Calendar 0 Table
SPI-4 Ingress Calendar 1 Table
N
P
Reserved
ENABLE
LP
LP
IDT IDT88K8483
Field
Field
Field
Note: (1)There are 128 table entries for SPI-4 main interface and 64 table entries for SPI-4 tributary interface.
Note: (1)There are 128 table entries for SPI-4 main interface and 64 table entries for SPI-4 tributary interface.
(2)The IDT88K8483 and the attached device must have identical calendars for ingress and the attached egress device.
(2)The IDT88K8483 and the attached device must have identical calendars for ingress and the attached egress device.
R/W
R/W
R
R/W
R/W
R/W
Read /
Read /
Read /
Write
Write
Write
Table 54 SPI-4 Ingress LP to LID Mapping Table (Block Base=0x0000, Register Offset=0x00-0xff)
Table 55 SPI-4 Ingress Calendar 0 Table (Block Base=0x0100, Register Offset=0x00-0x3f/0x7f)
Table 56 Ingress Calendar 1 Table (Block Base=0x0200, Register Offset=0x00-0x3f/0x7f)
0:0 - 0:5
0:7
0:7
0:6
0: 7
1:0
Bits
Bits
Bits
6
1
1
1
8
8
Length
Length
Length
0
0
0
0
0xFF
0xFF
Reset
Reset
Reset
State
State
State
105 of 162
LID number.This field maps the LP to the LID in the PFP and can take any 1 of 64
possible LID values. The LP number is the register offset. Refer to Figure 3 and Fig-
ure 4 for LID information.
Selects module A or module B ingress, valid for main.
0:Module A.
1:Module B.
Reserved bit.
Enables or disables this LP connection to the LID.
0:Disable.
1:Enable.
The LP value programmed schedules a status channel update according to the
calendar sequence.
The LP value programmed schedules a status channel update according to the
calendar sequence.
Description
Description
Description
October 20, 2006