IDT88K8483 Integrated Device Technology, IDT88K8483 Datasheet - Page 46

• Manufacturer Part Number: IDT88K8483
• Description: Spi-4 Exchange Document Issue 1.0
• Manufacturer: Integrated Device Technology

Tx Machine
complete. The interval between the end of a given transfer and the next payload control word consists of zero or more idle control words and training
patterns. Successive SOP must occur not less than 8 cycles apart.
transition on the interface. The adjacent device that generates the transfer have to meet the requirements as described in
transition state machine
Figure 18 Egress word transition state machine
is data for transmit. The LID to logical port mapping is configured by
not be mapped to the same logical port. LID can not be remapped in the IN_SYNCH status.
mode, the unit is one transfer, while In packet mode, the unit is one packet.
IDT IDT88K8483
Control words are inserted only between the transfers. Once a transfer has begun, the data words are sent uninterrupted until a whole transfer is
The SPI-4 interface loads data and overhead from the egress port buffer and generates transfer. The cycle to cycle behavior is described in
Packet mode and cut through mode selection is defined in PFP. The main SPI-4 transmit data from module A/B in round robin. In cut-through
If only one byte of the SPI-4 16 bit wide data is valid, then 8 LSB (B7 to B0) are fixed to 0.
control
aligne
Skew
Bit
p.46.
De-skew
TX machine
Figure 18 Egress word transition state machine
Figure 17 SPI-4 Egress State Block Diagram
p.46. The number of idle control words between transfers is less than or equal to 4 if there
termination
Status
Figure 18 Egress word transition state machine p.46
SPI-4 Ingress Training to out of sync threshold Register (p.
46 of 162
Locker
status
data
PFP
Figure 18 Egress word
October 20, 2006
111). Multiple LID can
shows the word