RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 64

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

3.0 Circuit Descriptions
3.5 HDSL Channel
3.5.2.6 Receive Payload
Figure 3-25. HDSL Auxiliary Receive Payload Timing
3-32
3.5.2.7 HDSL Auxiliary
3.5.2.4 CRC Checking
RAUX
BCLK
3.5.2.5 HOH Demux
ROH
ROH
4-bit STUFF
1
Receive
Mapper
2
3
4
5
The Cyclic Redundancy Check (CRC) error is reported each time the calculated
CRC of the (N)th HDSL frame does not match the CRC received in the (N+1)th
HDSL frame. Individual block errors are reported in CRC_ERROR [STATUS_2;
addr 0x06] and are accumulated in CRC_CNT [addr 0x21]. Each HDSL receiver
calculates CRC in the same manner as described for the transmitter.
HDSL Overhead (HOH) bits are grouped into the following categories: SYNC,
IND, EOC, CRC, and Z-bits. (Refer to
frame.) HOH demux extracts IND, EOC, and Z-bits from each receive frame and
places them into MPU accessible read registers RIND, REOC, and RZBIT (see
Table
as noted. Otherwise, data is overwritten by new received data.
The receive payload mapper controls placement of receive payload bytes and
Z-bits into the RFIFO as programmed by the RMAP Registers [RMAP; addr
0x64]. The payload mapper aligns itself to incoming HDSL 6 ms frames and
selectively transfers payload bytes from the received payload block.
The HDSL auxiliary receive channels allow the system to monitor the receive
HDSL payload and overhead bits output from the descrambler on RAUXn. The
entire received HDSL unscrambled bit stream is output on RAUXn at the BCLKn
rate. The MPU selects which category of RAUXn data is marked by ROHn
according to programmed values for RAUX_EN and RAZ [CMD_6; addr 0xF3].
ROHn either marks all overhead bits (STUFF, SYNC, HOH, and Z-bits) as shown
in
system can externally decode ROHn to access specific payload bytes or overhead
bits, or to qualify receipt of the last 40 Z-bits. RAUXn and ROHn are disabled
(output low) when the respective RAUX_EN is inactive.
Payload Blocks
Figure
6
4-10). The MPU must read the contents of the HOH registers every 6 ms, or
7
3-25, or marks only the last 40 Z-bits, as shown in
8
9
14-bit SYNC
10 11 12
Conexant
Table 3-2
IND
for HOH bit positions within the
Z1
byte1
RS8953B/8953SPB
Figure
HDSL Channel Unit
RAUX_EN = 1
RAZ = 0
3-26. The
N8953BDSB