RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 42

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

3.0 Circuit Descriptions
3.2 PCM Channel
3.2.2 PCM Receive
Figure 3-9. PCM Receive Block Diagram
3-10
RMSYNC
DROP
RSER
RCLK
BER Meter
= Command Register Bit
BER_SEL
PP_LOOP
TMSYNC
Frame
Delay
The PCM receive formatter shown in
output according to receive combination table settings and the frame format
defined by the PCM Formatter Registers (see
operates on the clock edge selected by RCLK_SEL [CMD_2; addr 0xE6] and
references the PCM receive timebase and RSER frame location to the alignment
provided by the master HDSL channel’s receive 6 ms frame. Therefore, the
position of bit 0, frame 0 output on RSER, is slaved to the HDSL receiver
selected as master by MASTER_SEL [CMD_5; addr 0xE9]. The RSER timing
relationship with respect to PCM 6 ms sync is shown in
sync is created from the HDSL 6 ms frame delayed by the programmed
RFIFO_WL [addr 0xCD] value, as shown in
TSER
Delay
Bit
PCM Receive Timebase
Combine Table
Length
MF
Conexant
Length
Frame
DBANK 2
DBANK 3
DBANK 1
SIG Table
Count
MF
RFIFO 1
RFIFO 2
RFIFO 3
Figure 3-9
RCLK_INV
RX_RST
Figure
Table
RFIFO_WL
constructs the serial data (RSER)
FROM CH1 RMAP
FROM CH2 RMAP
FROM CH3 RMAP
4-4). The PCM receiver
3-13.
RCLK_SEL
MASTER_SEL
Figure
RS8953B/8953SPB
HDSL Channel Unit
3-10. PCM 6 ms
CH1 RSYNC
CH2 RSYNC
CH3 RSYNC
DPLL RCLK
EXCLK
TCLK
N8953BDSB