RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 31

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
Table 2-2. Signal Definitions (3 of 4)
N8953BDSB
RMSYNC
TMSYNC
MSYNC
Signal
EXCLK
RSER
RCLK
TSER
TCLK
Multiframe Sync
Multiframe Sync
Transmit Master
Transmit Clock
Transmit Serial
External Clock
Receive Serial
Receive Clock
Transmit
Receive
Name
Sync
Data
Data
I/O
I
I
I
I
(2)
O
(2)
(1)
O
(1)
O
O
Operates at the PCM bit rate and samples the PCM transmit inputs: TSER,
TMSYNC, and INSDAT; and clocks the PCM transmit output, INSERT. Falling
edge samples and rising edge outputs are normal, inverted TCLK edges are
selectable. Optionally, RCLK or EXCLK can be programmed as the PCM transmit
clock for loopback or externally timed applications.
Operates at the PCM bit rate and clocks the PCM receive outputs: RSER,
RMSYNC, and DROP. Normally, RCLK is supplied by the internal clock recovery
DPLL. Optionally, EXCLK or TCLK can be programmed as the receive source
during loopback or externally timed applications. Rising-edge (normal) or
falling-edge (inverted) output transitions are selectable.
Optionally sources the PCM Receive Clock (RCLK), or both RCLK and PCM
Transmit Clock (TCLK) for systems that supply a local master clock. Normal or
inverted edges are also selectable.
Accepts up to 64 timeslots (1 timeslot = 8 bits) of data and an optional framing
bit per PCM frame. TSER data and F-bits are then routed and mapped into the
HDSL transmit channel payload.
Outputs up to 64 timeslots of data and an optional F-bit per PCM frame. Receive
serial data and F-bits are constructed by mapping and combining payload from
the HDSL receive channels.
Active-high input resets the PCM transmit time base during framed applications.
TMSYNC is ignored in unframed or asynchronously mapped applications. The
low to high input state transition is detected and internally delayed by a
programmable bit and frame offset to coincide with the TSER and INSDAT
sample location of bit 0, frame 0. The programmable sample point
accommodates any system’s rising edge frame or multiframe sync signal.
Active-high output from the receive timebase, typically programmed to mark
PCM multiframe boundaries during framed applications, and remains unused
during unframed or asynchronously mapped applications. RMSYNC pulses high
for one RCLK coincident with RSER output of bit 0, frame 0. Bit 0 is the first bit
in TS0 of an E1 or Nx64 frame, or the F-bit of a T1 frame. Programmable bit and
frame delays allow RMSYNC to mark any desired RSER bit.
Active-high output pulses high for one TCLK to mark two clock cycles before the
TSER and INSDAT sample point of bit 0, frame 0, of a transmit multiframe.
MSYNC references the TMSYNC applied by the system or supplies the system
with a master PCM frame/multiframe sync signal.
PCM Channel
Conexant
Description
2.0 Pin Descriptions
2.2 Signal Definitions
2-9