RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 103

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
4.9 DPLL Configuration
Table 4-6. DPLL Configuration Write Registers
The DPLL synthesizes the PCM Receive Clock (RCLK) output from the 60 through 80 MHz Reference Clock
(HFCLK) generated internally by PLL multiplication of MCLK, or input directly on MCLK [see PLL_MUL
and PLL_DIS in CMD_1; addr 0xE5]. HFCLK must operate in the 60 to 80 MHz frequency range, but requires
no specific phase or frequency relationship to the PCM or HDSL channels. The nominal frequency (f
RCLK is synthesized by setting the DPLL_FACTOR and DPLL_RESID values according to the integer and
fractional results of the following formula:
HFCLK divided by PLL scale factor:
N8953BDSB
0xD5—DPLL Residual (DPLL_RESID_LO)
Address
The DPLL phase detector operates from the 10–15 MHz General Purpose Clock (GCLK) which equals
0xD5
0xD6
0xD7
0xD8
0xDB
0xF6
7
DPLL_RESID_LO
DPLL_RESID_HI
Register Label
DPLL_FACTOR
DPLL_GAIN
DPLL_PINI
DPLL_RST
6
where: f
5
Bits
—
8
8
8
7
8
f
INTEGER
FRACTION = Fractional part of result [DPLL_RESID; addr 0xD5]
PLL_MUL
PLL_DIV
[INTEGER.FRACTION]
GCLK
MCLK
PCM
DPLL Residual
DPLL Residual
DPLL Factor
DPLL Gain
DPLL Phase Detector Init (optional for RS8953B)
DPLL Phase Detector Reset
=
4
DPLL_RESID[7:0]
Conexant
f
-------------------------------------------------
MCLK
= MCLK input frequency
= RCLK output frequency desired
= Integer part of result [DPLL_FACTOR; addr 0xD7]
= PLL multiplication factor [CMD_1; addr 0xE5]
= PLL scale factor [CMD_1; addr 0xE5]
PLL_DIV
PLL_MUL
3
=
f
------------------------------------------------ -
MCLK
Name/Description
2
2
PLL_MUL
f
PCM
1
4.9 DPLL Configuration
4.0 Registers
PCM
0
) of
4-35