RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 38

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

3.0 Circuit Descriptions
3.2 PCM Channel
Figure 3-5. PCM Transmit Sync Timing
Figure 3-6. PCM Transmit Data Timing
3-6
NOTE(S):
Mframe
MSYNC
Frame
PCM
PCM
PCM
Bit
3.2.1.1 Transmit
Synchronization
TCLK falling edge samples and rising edge outputs shown per TCLK_SEL = 00
TMSYNC
INSDAT
TMSYNC
MSYNC
TSER
TCLK
0 1
M
when TFRAME_LOC is equal to 0.
MSYNC with increasing bit and frame delays.
NOTE:
Alignment of transmit PCM data in relation to MSYNC determines whether PCM
and HDSL frames are synchronously mapped. The RS8953B does not examine
transmit data for T1, E1, or application framing patterns. Therefore, the system
must apply PCM data aligned to MSYNC when synchronous mapping is desired.
transmit router guarantees that each PCM timeslot placed in the TFIFO will be
aligned and mapped into a specific HDSL payload byte. In addition, timeslots
from the first PCM frame are mapped to payload bytes in the first HDSL payload
block, and the start of a PCM multiframe is aligned with the start of an HDSL
frame.
Frame 0
0
0
Figure 3-5
If the system applies PCM bit 0, frame 0 coincident with MSYNC, then the
TFRAME_LOC[M] = MSYNC Bit Delay
1
N
MSYNC can optionally mark the start of every PCM frame (bit 0, all
frames) by setting MF_LEN equal to 1 frame per multiframe.
X
TMF_LOC[N] = MSYNC Frame Delay
FRAME_LEN[X] = PCM Frame Length
shows the phase relationship between TMSYNC and MSYNC
Frame Y
0
Mframe 0
TFRAME_LOC=0, TMF_LOC=0
FRAME_LEN[X]
Conexant
1
Sample PCM Bit 0 or F-bit, of Frame 0
2
MF_LEN[Y] = PCM Multiframe Length
MF_CNT[Z] = Mframes per 6 ms period
Figure 3-6
X
Mframe 1
illustrates the progression of
RS8953B/8953SPB
Mframe Z
HDSL Channel Unit
N8953BDSB