RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 35

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
3.1.3 Interrupt Request
3.1.4 Hardware Reset
N8953BDSB
The open-drain interrupt request output (INTR*) indicates when a particular set
of transmit, receive, or common status registers have been updated. Eight
maskable interrupt sources are requested on the common INTR* pin:
HDSL channel’s 6 ms frame. The basic structure of each interrupt source is
shown in
[IMR; addr 0xEB], where writing a 1 to an IMR bit prevents the associated
interrupt source from activating INTR*; Interrupt Request Register [IRR; addr
0x1F], where active interrupt events are indicated by IRR bits that are read high;
and Interrupt Clear Register [ICR; addr 0xEC], where writing a 0 to an ICR bit
clears the associated IRR bit, and if no other interrupts are pending, deactivates
INTR*. Error interrupts (TX_ERR and RX_ERR) are combined from multiple
sources, each source having its own interrupt enable. Individual errors are
reported in the common Error Status Register [ERR_STATUS; addr 0x3C] which
is cleared by an MPU read.
Assertion of hardware reset (RST*) is required to preset all IMR bits, clear all
error interrupt enables, and thus disable INTR* output. For backward
compatibility with Bt8953 software, RST* also clears the command register bits
added to RS8953B which aren’t present on prototype Bt8953. All other registers
are MPU accessible while RST* is asserted.
1.
2.
3.
4.
5.
6.
7.
8.
All interrupt events are edge-sensitive and synchronized to their respective
TX1 = Channel 1 Transmit 6 ms Frame
TX2 = Channel 2 Transmit 6 ms Frame
TX3 = Channel 3 Transmit 6 ms Frame
RX1 = Channel 1 Receive 6 ms Frame
RX2 = Channel 2 Receive 6 ms Frame
RX3 = Channel 3 Receive 6 ms Frame
TX_ERR = Logical OR of 3 Transmit Channel Errors
RX_ERR = Logical OR of 3 Receive Channel Errors and DPLL Errors
Figure
3-2, with three associated registers: Interrupt Mask Register
Conexant
3.0 Circuit Descriptions
3.1 MPU Interface
3-3