RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 111

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
DBANK_SEL[1:0]
Applicable only to the LTU grooming site in a 2E1 or 3E1 Point-to-Multipoint (P2MP) system, the receive
signaling table assembles E1 Timeslot 16 (TS16) from the ABCD signaling supplied by the three remote sites.
Signaling from each channel is located by RSIG_TBL selection of a particular timeslot in the receive
combination table, and automatically sampled when RSIG_EN [CMD_6; addr 0xF3] is active. The groomed
signaling table output replaces the DBANK_3 register selection in the receive Combination Table
[COMBINE_TBL; addr 0xEE].
RSIG_WR [CMD_3; addr 0xE7] to reset the table pointer to zero, and then by writing up to 16 entries
sequentially to RSIG_TBL. The RS8953B increments the table pointer after each write cycle to the RSIG_TBL
address. The first table entry corresponds to the first E1 frame (frame 0) output on RSER and corresponds to
subsequent entries to successive frames. Each entry contains two identical RSIG[1:0] grooming codes which
select the HDSL channel source for ABCD signaling bits during the respective frame. For example, frame 1
grooming codes select ABCD for E1 channels 1 and 17, frame 2 selects ABCD for E1 channels 2 and 18, and
so on. Grooming codes for E1 frame 0 are similar to other E1 frames, and allow the system to select which
HDSL channel supplies the CAS Multiframe Alignment Signal (MAS) and which channel supplies the extra
and multiframe yellow alarm bits (XYXX). RS8953B does not provide access to the actual received TS16 data
and assumes that EOC messages or indicator bits are used to report far-end alarm and status information.
RSIG[1:0]
N8953BDSB
0xF2—Receive Signaling Table (RSIG_TBL)
MPU access to the receive signaling table is provided through the RSIG_TBL register by first setting
—
7
Data Bank Select (Applicable only if COMBINE = 00)—Selects one of three DBANK
registers to output on RSER during the respective timeslot.
Receive Signaling Grooming Code—Selects which HDSL channel supplies ABCD signaling,
MAS, or XYXX bits for output on RSER during the PCM timeslot selected by receive
combination table. Sixteen table entries correspond to E1 frames 0 through 15, where the most
significant grooming code corresponds to the first four bits of the TS16 output.
—
6
—
5
DBANK_SEL[1:0]
RSIG[1:0]
RSIG_EN
00
01
10
11
00
01
10
11
—
0
1
4
Conexant
3
RSIG[1:0]
Determined by COMBINE[1:0]
HDSL Channel 1
HDSL Channel 2
HDSL Channel 3
Source of RSER Output Data
None (invalid)
Determined by RSIG_EN
TS16 Source
DBANK_1; addr 0xDC
DBANK_2; addr 0xDD
DBANK_3; addr 0xDE
RSIG_TBL; addr 0xF2
2
RSER Source
1
4.10 Data Path Options
RSIG[1:0]
4.0 Registers
0
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