RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 32

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

2.0 Pin Descriptions
2.2 Signal Definitions
Table 2-2. Signal Definitions (4 of 4)
2-10
DROP
INSDAT
INSERT
MCLK
SCLK
VEXT
PLLVCC
PLLDGND
PLLAGND
VCC
GND
TCK
TMS
TDI
TDO
NOTE(S):
(1)
(2)
(3)
Signal
Internal pull-ups (80-100 kW) are present on inputs to allow unused inputs to remain disconnected.
Internal pull-downs (80-100 kW) are present on inputs to allow unused inputs to remain disconnected.
The pins do not perform these functions in RS8953SPBEPF and RS8953SPBEPJ.
Drop Indicator
Insert Data
Insert Indicator
Master Clock
System Clock
External Voltage
PLL Power
PLL Ground
PLL Analog
Ground
Power
Ground
Test Clock
Test Mode Select
Test Data Input
Test Data Output
Name
I/O
I
I
I
O
(1)
O
O
(1)
(1)
O
I
I
I
I
I
I
I
I
Active-high output indicates when specific PCM timeslots are present on RSER.
DROP is high for 8 bits coincident with each marked timeslot, or 1 bit when
marking F-bits. Any combination of timeslots and F-bits within the PCM frame
can be marked.
Alternate source of PCM transmit serial data. INSDAT is sampled by TCLK and
replaces TSER when INSERT is active. INSDAT and TSER use the same frame
format. INSDAT can be programmed to replace TSER data on a
per-timeslot-basis.
Active-high output indicates when specific INSDAT timeslots are sampled.
INSERT is high for 8 bits coincident with each marked timeslot or for 1 bit when
marking F-bits. Any combination of timeslots and F-bits within the PCM frame
can be marked.
Runs through a multiplier PLL to create an internal 60–80 MHz reference clock
for the DPLL. The 16 times symbol rate clock from a Conexant HDSL transceiver
typically connects to MCLK. However, MCLK is not required to be synchronized
to any HDSL or PCM channel. The DPLL reference clock is used to synthesize
the PCM Recovered Clock (RCLK) based on DPLL programmed values.
Optionally, a 60–80 MHz clock can be input directly on MCLK.
The internal 60–80 MHz DPLL reference clock is divided by 4 to create a
15–20 MHz system clock output on SCLK. SCLK can be applied to other devices
requiring a system clock (i.e., Bt8360 or Bt8510).
Used to bias input protection diodes. If interfacing to 5 V powered devices,
connect this pin to 5 V. Otherwise, connect 3.3 V to this pin.
3.3 Vdc +/– 0.3 V power input for the PLL.
0 Vdc ground reference for the PLL.
0 Vdc analog ground reference for the PLL. Tied to GND unless PLL operation is
desired above 80 MHz.
3.3 Vdc +/– 0.3 V power input.
0 Vdc ground reference.
Boundary scan clock samples and outputs test access signals.
Active-high enables test access port. Sampled by TCK rising edge.
Serial data for boundary scan chain. Sampled by TCK rising edge.
Outputs serial data from boundary scan chain on TCK falling edge.
DPLL and Power
Conexant
Drop/Insert
Description
RS8953B/8953SPB
HDSL Channel Unit
N8953BDSB