RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 41

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
Figure 3-8. TFIFO Water Level Timing
N8953BDSB
NOTE(S):
1. PCM and HDSL shown synchronously mapped (PCM_FLOAT = 0).
2. Equal TFIFO_WL settings provide minimum differential delay.
3.2.1.5 TFIFO Water
MSYNC
PCM
HDSL
(CH1)
HDSL
(CH2)
HDSL
(CH3)
(Bit)
Levels
0
1 2 3 4 5 6 7 8 9 10
CH1; TFIFO_WL[X]
CH2; TFIFO_WL[Y]
Each HDSL transmit channel aligns the start of its output frame with respect to
the PCM 6 ms sync according to the programmed TFIFO water level values
[TFIFO_WL; addr 0x05]. PCM 6 ms sync is created from MSYNC by the divisor
programmed in MF_CNT [addr 0xC7]. The HDSL 6 ms frame is created from
PCM 6 ms by adding the TFIFO_WL phase offset programmed for each channel,
as shown in
frame timing regardless of whether the system chooses to synchronize PCM data
to MSYNC.
TFIFO_WL as the number of TCLK cycle delays from the start of PCM 6 ms
sync to the start of HDSL 6 ms frame. Thus, this phase offset determines the
amount of PCM data written to the TFIFO before the HDSL transmitter begins
extracting data from the TFIFO, which also defines each transmitter’s data
throughput delay and subsequently the differential delay with respect to other
HDSL channels. The actual phase offset varies over time as a result of stuff bit
insertion as well as PCM and HDSL clock jitter and wander. Therefore,
TFIFO_WL is only used to establish the initial phase offset between PCM and
HDSL frames when the MPU issues the TFIFO_RST [addr 0x0D] command, or
after a stuffing error.
the system must consider transmit routing table assignments and other data path
delays when programming TFIFO_WL values. Sufficient phase offset must be
established to allow time for the first programmed timeslot to be routed from the
PCM frame into the TFIFO, to absorb the phase offset created by HDSL
overhead, to stuff bit insertion and clock frequency variation, and to unload the
first timeslot from the TFIFO and map data into the HDSL payload byte.
Conversely, to avoid TFIFO overflow, phase offset must be limited so the amount
of data residing in the TFIFO does not exceed the number of PCM bits routed
during one PCM frame, the maximum TFIFO depth (186 bits), or the total HDSL
payload block length [HFRAME_LEN; addr 0xCA].
CH3; TFIFO_WL[Z]
The phase offset between PCM and HDSL 6 ms frames is programmed by
Because all or part of the PCM frame can be routed to each HDSL channel,
Figure
X
16-bit SYNC + HOH
Differential
3-8. In this manner, HDSL output frames are slaved to PCM
Conexant
Delay
Y
16-bit SYNC + HOH
Z
16-bit SYNC + HOH
Z
byte1 from TFIFO1
Z
byte1 from TFIFO2
Z
byte1 from TFIFO3
3.0 Circuit Descriptions
byte2
byte2
3.2 PCM Channel
3-9