CN8330EPJD Conexant Systems, Inc., CN8330EPJD Datasheet

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CN8330EPJD

Manufacturer Part Number
CN8330EPJD
Description
Service SAR controller
Manufacturer
Conexant Systems, Inc.
Datasheet

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Data Sheet
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The CN8330 is an integral DS3/E3 framer designed to support the transmission
formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751
standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T
PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a
High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing
overhead.
E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be
enabled to reduce jitter on the incoming data. Transmit and receive data is available to
the host in either serial or parallel byte and nibble formats. Access is provided to the
terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in
T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations
(LCVs), parity errors, and Far End Block Errors (FEBEs).
control modes. The microprocessor control mode monitors all status conditions and
provides configuration control. The stand-alone monitor mode allows the CN8330 to
operate as a monitor providing status and alarm information on external pins.
Functional Block Diagram
RXNEG
DS3CKI
RXPOS
TXNEG
TXPOS
TCLKO
AD[7:0]
Control
TXCKI
The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751
Two operational modes are available: microprocessor and stand-alone monitor
Microprocessor
Loopback
Loopback
Source
Line
Interface
M
U
X
M
U
X
Conversion
Encoder
Unipolar
Bipolar
To/From
All Blocks
Overhead
Framing/
Insertion
Bypass
Enable
FIFO
FIFO
Processing
Transmitter
Overhead/
Processing
Recovery
Data Link
Overhead/
Data Link
Framing
Receiver
PPDL
PPDL
RXMSY
CBITO
RXCCK
RXDAT
RXCLK
Status
TXBCK
TDAT[7:0]
TXCCK
CBITI
RDAT[7:0]
RXBCK
Status
TXCKI
TXDATI
TXSYI
Distinguishing Features
• Supports DS3/E3 framing modes
• Includes high-speed HDLC controller
• Framing recovery for M13, C-bit
• Serial or parallel (octet or nibble)
• Average reframe time of less than
• Supports the LAPD terminal data link
• 68-pin PLCC or 80-pin MQFP
• Operates from a single +5 VDC ±5%
• Low-power CMOS technology
Applications
• Digital PCM switches
• Digital Cross-Connect Systems
• Channel Service Units (CSUs)
• Channel extenders
• ATM Switches/Concentrators
• PBXs
• Switched Multimegabit Digital
• Test equipment
• Routers (including HSSI ports)
(52 MHz)
parity, Syntran, and G.751 E3 signals
interface modes
1 ms for DS3 and less than 250 µs
for E3
and FEAC channel as defined in
T1.107a-1989
surface-mount package
power supply
Service (SMDS) Equipment
October 13, 1999
100441E

Related parts for CN8330EPJD

CN8330EPJD Summary of contents

Page 1

CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller The CN8330 is an integral DS3/E3 framer designed to support the transmission formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751 standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T ...

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... Ordering Information Model Number CN8330EPJD 68-Pin Plastic Leaded Chip Carrier (PLCC) CN8330EPD 80-Pin Metric Quad Flat Pack (MQFP) CN8330 Typical DS3 Application 31.6 RLINE1P RLINE1N 31.6 TLINE1P 37.4 37.4 0.01 TLINE1N Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use ...

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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 4.0 Mechanical/Electrical Specifications Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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DS3/E3 Framer with 52 Mbps HDLC Controller Conexant CN8330 100441E ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller List of Figures Figure 1-1. CN8330 Pinout Diagram - 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures vi DS3/E3 Framer with 52 Mbps HDLC Controller Conexant CN8330 100441E ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller List of Tables Table 1-1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables viii DS3/E3 Framer with 52 Mbps HDLC Controller Conexant CN8330 100nnnx ...

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Product Description The CN8330 is a frame synchronization, recovery, and signal generation circuit. Applications for digital terminals include digital cross-connect systems, customer premise multiplexers, channel extenders, network managers, PBXs, Switched Multimegabit Digital Service (SMDS) equipment, and monitor or test ...

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Product Description Configuration, control, and monitoring of the CN8330 termination circuit and framer are accomplished with a selectable microprocessor control mode that monitors all status conditions and provides configuration control. In DS3 mode a stand-alone mode of operation is ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 1.1 Pin Descriptions The CN8330 Framer is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC) and an 80-pin Metric Quad Flat Pack (MQFP) and shown in Figure 1-2 Table diagrams of ...

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Product Description 1.1 Pin Descriptions Figure 1-2. CN8330 Pinout Diagram - 80-Pin MQFP 1-4 DS3/E3 Framer with 52 Mbps HDLC Controller NC 1 GND 2 FIFEN 3 VCO 4 RXPOS 5 RXNEG 6 DS3CKI 7 RXCKI ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Table 1-1. Pin Descriptions Pin Pin (68-Pin (80-Pin Pin Label PLCC) MQFP GND 2 73 AD[7]/FRMERR 3 74 AD[6]/LCV 4 75 AD[5]/PAR 5 76 AD[4]/IDLE 6 77 AD[3]YEL 7 78 ...

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Product Description 1.1 Pin Descriptions Figure 1-3. CN8330 Framer Functional Logic Diagram - 68-Pin PLCC Rx Bipolar Pos I Rx Bipolar Neg I Rx Line Clock In I Dejittered Clock In I FIFO Enable I Tx Clock In I ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Figure 1-4. CN8330 Framer Functional Logic Diagram - 80-Pin MQFP Rx Bipolar Pos Rx Bipolar Neg Rx Line Clock In Dejittered Clock In FIFO Enable Tx Clock In Tx C/N Bit Serial ...

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Product Description 1.1 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label ALE/PAREN Address Latch Enable/Parallel Input Enable CS/ALM0 Chip Select/Alarm 0 RD*/ALM1 Read/Alarm 1 WR*/CRC32 Write/Cycle Redundancy Check 32 MON/MIC* Monitor/Microprocessor Mode Select AD[0]/LOS Address-Data ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Table 1-2. Hardware Signal Definitions ( Pin Label AD[4]/IDLE Address-Data 4/Idle Code Detection AD[5]/PAR Address-Data 5/Parity Error Detection AD[6]/LCV Address-Data 6/Line Code Violation AD[7]/FRMERR Address-Data 7/ Frame Bit Error CNTINT/LINELB ...

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Product Description 1.1 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label TCLKO Transmit Clock Out TXPOS, TXNEG Transmit Bipolar Positive, Negative TDAT[3:0] Transmit Data Bits 3–0 (Bit 0 is the LSB) TDAT[4]/LCVERRI Transmit Data Bit ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Table 1-2. Hardware Signal Definitions ( Pin Label DS3CKI DS3 Receive Line Clock In RXPOS, RXNEG Receive Bipolar Positive/Negative RXCKI Receive Dejittered Clock In FIFEN FIFO Enable RXDAT Receive Serial ...

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Product Description 1.1 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label RDAT[3]/IDLE Receive Data Byte 3/Idle Code Detection RDAT[4]/ Receive Data Byte 4/Frame FRMERR Error Detection RDAT[5]/ Receive Data Byte 5/Line LCVCAR Code Violation Carry ...

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Functional Description 2.1 Overview 2.1.1 Brief Block Description A block diagram of the circuit is illustrated in B3ZS/HDB3 signal is decoded and the bipolar input is converted to a unipolar, clocked serial data stream. Frame bit content is checked ...

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Functional Description 2.1 Overview Figure 2-1. Functional Block Diagram RXPOS RXNEG DS3CKI MUX TXPOS TXNEG TXCKI SOURCELB RXCKI FIFEN Control Microprocessor Interrupts Interface Address/Data Control CBITI Framing and TXCCK Overhead Bit Insertion TXSYO TXNRZ Data FIFO Data MUX for ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.1.2 Clock Interface and Initialization The CN8330 clock input (TXCKI) controls the transmitter. This input should be supplied with a 44.736 MHz clock in DS3 mode and a 34.368 MHz clock in ...

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Functional Description 2.1 Overview 2.1.3.2 Microprocessor There are two separate interrupt pins that can be connected to the microprocessor Interrupts (or microcontroller): Counter and Data Link. The counter interrupt pin (CNTINT/LINELB) combines seven sources of interrupts on an external ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.2 Line Interfaces 2.2.1 Transmitter Line Interface The transmitted line signals are shown in output sequence are shown. Separate signal pins provide the appropriate output signal for positive and negative pulses. The ...

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Functional Description 2.2 Line Interfaces 2.2.2 Receiver Line Interface The line interface for the receive bipolar signals consists of two logic-level signals that represent the positive and negative bipolar line pulses (RXPOS, RXNEG) and an input (DS3CKI) for an ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.3 Transmitter Operation The transmitter circuit is synchronized to the transmit input data by an external synchronization signal. The external synchronization signal sets the M-frame reference for transmitted signals. 2.3.1 Input and ...

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Functional Description 2.3 Transmitter Operation If the TDAT[7]/TXSYI M-frame sync signal is provided sampled on the rising edge of TXCKI and should have a low-to-high transition from the last bit of the M-frame (bit 680 of subframe ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Figure 2-5. Transmitter Timing for Parallel DS3 Mode TXCKI TXSYO TXBCK/ TXGAPCK Data TDAT[7:0] Subframe 7 2.3.3 E3 Mode The clock and data edges for E3 mode have the same relationship as ...

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Functional Description 2.3 Transmitter Operation Figure 2-6. Transmitter Timing for Serial E3 Mode TXCKI VALFCS/ TXOVH TXBCK/ TXGAPCK TXSYO TDAT[6]/TXDATI 1520/1524 Info Bits (Serial In) TDAT[7]/TXSYI (Sync In) 2.3.4 Framing Bit Generation In DS3 mode, all F and M ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller In E3 mode, the FAS pattern is automatically generated by the transmitter circuitry. The transmitter also inserts the A-bit as determined from the Transmit Alarm Control 1 bit [TxAlm1;CR00.5] and the N-bit ...

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Functional Description 2.3 Transmitter Operation In C-bit parity mode with internal sourcing of the C-bits, FEBE alarms are generated automatically in the transmitter when the receiver detects either a frame bit error or a C-bit parity error in an ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller If the framer mode that allows data link transmission as described previously, then the Terminal Data Link Control Register is the main control register used for transmit data link ...

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Functional Description 2.3 Transmitter Operation When this set of controls is latched, the processor will be interrupted. At this time, a new message may be sent, or the TxMsg bit may be set to zero to send idle flags. ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.3.6.4 Transmitter This example will show the sequence necessary to transmit a 10-byte hex Control Example message starting in the low half of the transmit buffer. With the transmitter in the idle ...

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Functional Description 2.3 Transmitter Operation The Transmit FEAC Channel Byte Register controls the byte to be transmitted on the TxFEAC channel. All messages for transmission on this channel must be in the form “0xxxmmm011111111". The rightmost bit of this ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller HDLC mode is selected by setting the ParaEn bit of the Feature Control Register high and the DisPPDL bit of the PPDL Control Register low. Operation is controlled by the SNDMSG and ...

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Functional Description 2.3 Transmitter Operation TXBCK/TXGAPCK is generated from TXCKI and has a duty cycle of 25 percent. TXBCK will nominally be one-eighth the TXCKI frequency but is influenced by HDLC transparency bit insertions and DS3/E3 overhead bits. In ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller The PPDL transmitter can be used with a nibble-wide interface for DS3 SMDS applications if desired. To enable nibble-wide transmission, both the Nibble Mode Enable [Nibble;CR05.0] and DisPPDL bits in the PPDL ...

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Functional Description 2.3 Transmitter Operation FCS calculation can be limited to the first N bytes of the transmitted message by setting the Limit Frame Check Sequence Calculation [LimitFCS;CR05.3] control bit. In this mode, the FCS is calculated on the ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.3.11 Test Equipment Specific Features Additional features in the transmitter are available if parallel mode is not selected (ParaEn = 0). The RDAT[7]/TXNRZ pin becomes an output of the transmit data in ...

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Functional Description 2.4 Receiver Operation 2.4 Receiver Operation 2.4.1 Bipolar-to-Unipolar Conversion The bipolar-to-unipolar recovery circuit includes the B3ZS/HDB3 decoding circuit. Decoding is done according to TR-TSY-000009 for B3ZS or G.703 for HDB3. A circuit detects the B3ZS/HDB3 signature and ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.4.3 Received Signal Output The received unipolar signal is recovered and provided with a clock on RXDAT and RXCLK. An M-frame synchronization signal and gapped clock are also provided. propagation delays for ...

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Functional Description 2.4 Receiver Operation Figure 2-12 mode is enabled by setting the ParaEn bit in the Feature Control Register and setting the DisPPDL bit in the PPDL Control Register. The receive data is valid on either the rising ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.4.4 Framing Operation In DS3 mode, a parallel search framing circuit is used to recover the subframe and M-frame alignments in the DS3 signal. Framing is initiated by an Out-of-Frame (OOF) condition ...

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Functional Description 2.4 Receiver Operation The frame bits are monitored to determine errors and OOF conditions. The OOF indicator is set whenever consecutive F framing bits are in error or when consecutive M-frames ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller The receiver powers indeterminate state initialized by the receipt of an idle flag (0x7E) on the link, which sets RxIdle = 1 in the Terminal Data Link ...

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Functional Description 2.4 Receiver Operation 2.4.6.1 Receiver The data link receiver generates an interrupt in response to three events: the Interrupts current half of the message buffer is full, the end-of-message flag was detected abort flag was ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.4.7 RxFEAC Channel Reception Receiver logic is provided for reception of the Receive Far End Alarm and Control (RxFEAC) Channel which is present in C-bit parity mode. This channel uses a bit-oriented ...

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Functional Description 2.4 Receiver Operation 2.4.8 PPDL Receiver The receiver circuitry contains a PPDL receiver for the payload portion of the CN8330 data that is activated when the ParaEn bit in the Feature Control Register is set. This receiver ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Timing for this operation is shown in Illustrated are cases of a good packet received, a packet received with a bad FCS, and an aborted packet. Each packet is shown with one ...

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Functional Description 2.4 Receiver Operation The parallel interface can be used without transparency bit deletion by setting the DisPPDL bit in the PPDL Control Register this mode, byte synchronization in the transmitter and receiver is ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.4.10 Serial C-Bit Output All received C-bits are output on the CBITO pin on the rising edge of RXCCK/TZNRZ in DS3 mode. This allows external circuitry to examine individual C-bits if necessary. ...

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Functional Description 2.5 Monitor Mode for Stand-Alone Operation 2.5 Monitor Mode for Stand-Alone Operation Operation without a microprocessor is possible with the MON/MIC* pin tied high. In this mode of operation, the transmitter is set to M13 format with ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 2.5.1 DS3 Monitor Mode Error Outputs If stand-alone monitor mode is selected by tying the MON/MIC* pin high, then the CN8330 operates without a microprocessor and the eight address/data pins (AD[7:0]) of ...

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Functional Description 2.5 Monitor Mode for Stand-Alone Operation 2-36 DS3/E3 Framer with 52 Mbps HDLC Controller Conexant CN8330 100441E ...

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Registers For a summary of all registers, refer to the Register Summary section at the end of this chapter. 3.1 Control Registers 0x00—Mode Control Register (CR00 LineLp SourceLp TxAlm1 Line Loopback Enable—Set to enable the ...

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Registers 3.1 Control Registers External Overhead Insert—Set enable insertion of the overhead bits (DS3 ExtOvh and F or E3: FAS, A, and N) from the transmit serial data stream. External C-Bit Insert—Used ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 0x01—Terminal Data Link Control Register (CR01) This Terminal Data Link Control Register controls functions of the terminal data link as defined in C-bit parity or E3 mode. If C-bit parity or E3 ...

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Registers 3.1 Control Registers Disagreement Counter Interrupt Enable—A control bit that allows interrupts from the DS3 DgrCtrIE Disagreement Counter [SR08;0x21]to appear on the CNTINT/LINELB output pin. Parity Error Counter Interrupt Enable—A control bit that allows interrupts from the DS3 ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller FEBE Pattern Bit Field—Set to the 3-bit sequence that sent each time a FEBE FEBEC[3:1] indication transmitted in C-bit parity mode. This pattern is automatically transmitted ...

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Registers 3.2 Status Registers 3.2 Status Registers There are six Status Registers: five for DS3/E3 status and one to indicate the version number of the IC. Also included is a shadow register for the DS3/E3 maintenance status to latch ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 0x11—Counter Interrupt Status Register (SR01) The Counter Interrupt Status Register contains status information about active interrupts needing service from the controller. This register needs to be read by the controller upon receiving ...

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Registers 3.2 Status Registers 0x12—Data Link Interrupt Status Register (SR02) The Data Link Interrupt Status Register contains information about active data link interrupts needing service from the controller. The controller determines the source of the data link interrupt by ...

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... This enables loading of version-specific software, if needed. The part number for the CN8330 framer is 0000. The version number is indicated below and will be incremented with any change in circuitry within the IC Part[3] Part[2] Part[1] U Conexent Part Number CN8330EPJC/CN8330EPFC CN8330EPJD/CN8330EPFD 100441E 4 3 RxByte[1] RxByte[ Part[0] Ver[3] Obsolete Base Number ...

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Registers 3.2 Status Registers 0x16—Shadow Status Register (SR06) The Shadow Status Register contains copies of the five least significant bits of the DS3/E3 Maintenance Status Register [SR00;0x10]. Whenever a status indication appears in the DS3/E3 Maintenance Status Register, the ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 0x20–0x26—DS3/E3 Error Counters There are six error counters for DS3/E3 errors located at addresses 0x20–0x26. All are 8-bit counters with the exception of the DS3 Disagreement [SR08;0x21] and DS3/E3 LCV Counters [SR12,SR13;0x25,0x26]. ...

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Registers 3.2 Status Registers 0x21—DS3 Disagreement Counter (SR08) The DS3 Disagreement Counter consists of two 4-bit counters. Both counters indicate 0 through 15 counts of disagreements in either the two X (yellow alarm) bits or the two P (parity) ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 0x24—DS3 FEBE Event Counter (SR11 DS3FEBE[7] DS3FEBE[6] DS3FEBE[5] DS3 FEBE Event Counter— Increments for each M-frame where any C-bit in subframe 4 DS3FEBE[7:0] is zero. 0x25,0x26—DS3/E3 LCV Counter—Low and ...

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Registers 3.3 Memory Registers 3.3 Memory Registers 0x30–0x37—Transmit Terminal Data Link Message Buffer (TxTDL) The Transmit Terminal Data Link Message Buffer locations are loaded with the message bytes to be sent on the terminal data link in response to ...

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Register Summary Table 3-1. Register Overview Register Read ADDR Label Write 0x00 CR00 R/W 0x01 CR01 R/W RxTDLIE 0x02 CR02 R/W 0x03 CR03 R/W TxFEAC[7] 0x04 CR04 R/W TstEqSel 0x05 CR05 R/W FCSCnt[3] Table 3-2. Status Registers (1 ...

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Table 3-2. Status Registers ( Register Read ADDR Label Write 0x21 SR08 R ParDgrCtr[3] 0x22 SR09 R FerrCtr[7] 0x23 SR10 R DS3PthCtr[7] 0x24 SR11 R DS3FEBE[7] 0x25 SR12 R LCVCtr[7] 0x26 SR13 R LCVCtr[15] Table 3-3. Transmit Terminal ...

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Mechanical/Electrical Specifications 4.1 Timing Requirements Table 4-1 interface. The parameter t This clock signal is used in the read circuit of the microprocessor to ensuring no status events are missed and that counter values are accurately read. Read operation ...

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Mechanical/Electrical Specifications 4.1 Timing Requirements Table 4-1. Microprocessor Interface Timing ( Symbol t ALE Low to RD*/WR* Low clcl t Data Stable Before WR* High ds t Data Hold after WR* High dh t Address/Select Hold after ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Figure 4-2 relationships for all output and input signals. Propagation delays for the output signals are listed below. The output signal timings are relative to the listed edge of the clock. Clock ...

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Mechanical/Electrical Specifications 4.1 Timing Requirements Table 4-3. Output Signal Timing Output Symbol RXCLK RXMSY RXDAT RXCCK CBITO RXOVH RXBCK RXGAPCK RXGAPCK RDAT[7] /TXNRZ TXPOS/TXNEG TXSYO TXGAPCK TXBCK TCLKO TXOVH Table 4-4. Input Setup/Hold Timing Input Symbol CBITI TDAT[7:0] (Parallel ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 4.2 Environmental Conditions 4.2.1 Power Requirements and Temperature Range Stresses above those listed as Absolute Maximum Ratings (see cause permanent damage to the device. This is a stress rating only, and functional ...

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Mechanical/Electrical Specifications 4.3 Electrical Characteristics 4.3 Electrical Characteristics 4.3.1 DC Characteristics All inputs and bidirectional signals have input thresholds compatible with TTL drive levels. All outputs are CMOS drive levels and can be used with CMOS or TTL logic ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Table 4-7. Output Drive Capability 100441E Output Pin RXCLK 22 IDLE 24 VALFCS 25 RDAT[ 32, 30, 29, 28, 27 CBITO 37 RXCCK 38 TESTO 41 TXCCK 46 ...

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Mechanical/Electrical Specifications 4.4 Mechanical Specifications 4.4 Mechanical Specifications Figure 4-3. 68–Pin Plastic Leaded Chip Carrier (J-Bend) .042" .048" X 45˚ PIN 1 IDENTIFIER INCHES MIN. NOM. MAX .165 .200 ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Figure 4-4. 80-Pin Metric Quad Flat Pack (MQFP) 100441E 4.0 Mechanical/Electrical Specifications 4.4 Mechanical Specifications S Y ALL DIMENSIONS IN M MILLIMETERS MIN. NOM. A 2.20 2.25 A1 ---- ...

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Mechanical/Electrical Specifications 4.4 Mechanical Specifications 4-10 DS3/E3 Framer with 52 Mbps HDLC Controller Conexant CN8330 100441E ...

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Appendix A Multimegabit HDLC Formatter A.1 Introduction The CN8330 was designed as a DS3/E3 framer with both serial and parallel data inputs. The circuit has an integral High-Level Data Link Control (HDLC) interface that can be used without the insertion ...

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Appendix A Multimegabit HDLC Formatter A.1 Introduction The receiver provides complementary operation, deriving byte-organized data and HDLC protocol status including FCS checking at serial rates Mbps. Figure A-1 illustrates the major data paths of the HDLC formatter. ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller A.2 Block and Logic Diagrams The transmit serial clock is applied to the TXCKI input of the HDLC transmitter. The circuit generates a byte clock and either idle code, a serialized message ...

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Appendix A Multimegabit HDLC Formatter A.2 Block and Logic Diagrams Figure A logic diagram showing the functional partitioning of the pins. This diagram pertains only to HDLC mode operation, for which some of the pins are reassigned from ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Figure A-3. HDLC Formatter Logic Diagram - 80-Pin MQFP 5 Receive Data Input I 6 Receive Data Input Receive Clock Input 8 Ground I 3 Ground I 56 Transmit ...

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Appendix A Multimegabit HDLC Formatter A.3 PPDL Transmitter A.3 PPDL Transmitter The PPDL transmitter is enabled by setting the Parallel Data Enable bit [ParaEn; CR04.3] in the Feature Control Register [CR04;0x04]. The PPDL formatter is controlled by signals applied on ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller The transmit byte clock (TXBCK) is generated from the transmit clock input (TXCKI) and has a duty cycle of 25 percent. TXBCK will nominally be one-eighth of the TXCKI frequency but is ...

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Appendix A Multimegabit HDLC Formatter A.3 PPDL Transmitter Timing for this operation is shown in packet received, a packet received with a bad FCS, and an aborted packet. Each packet is shown with one idle flag marking the end of ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller Figure A-5. PPDL Receiver Timing RXCLK RXBCK Data RDAT[7:0] FCS IDLE Good Packet VALFCS IDLE Packet w/Bad FCS VALFCS RDAT[7:0] Data IDLE Aborted Packet VALFCS 100441E Appendix A Multimegabit HDLC Formatter Data ...

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Appendix A Multimegabit HDLC Formatter Control Registers Control Registers 0x00—Mode Control Register (CR00) NOTE LineLp SourceLP Rsvd Line Loopback Enable—Set to enable the loopback in the external direction. This loopback LineLp connects the received data stream before ...

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CN8330 DS3/E3 Framer with 52 Mbps HDLC Controller 0x05—PPDL Control Register (CRO5) The PPDL Control Register is provided to control the mode of operation of the PPDL transmitter and receiver. NOTE FCSCnt[3] FCSCnt[2] FCSCnt[1] FCS Calculation Count—Determines ...

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Appendix A Multimegabit HDLC Formatter Control Registers A-12 DS3/E3 Framer with 52 Mbps HDLC Controller Conexant CN8330 100441E ...

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Appendix B This appendix describes the various non-conformances associated with this device. B.1 DS3CKI Clock Duty Cycle Conexant recommends a 60/40 percent duty cycle maximum for the DS3CKI input. B.2 Overhead Bit Insertion in E3 Parallel Payload Mode When the ...

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Appendix B B.3 HDLC Formatter Mode Support While Configured for E3 Framing B.3 HDLC Formatter Mode Support While Configured for E3 Framing This mode was previously selected by configuring the following bits: CR00.3=1 (E3Frm), CR04.3 (ParaEn) and CR05.1=0 (DisPPDL).If this ...

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Appendix C Here's what we've recommended as a starting point for those customers who need a jitter attenuation PLL for TBR24 compliance in E3 mode. An external jitter attenuation PLL can be implemented for CN8330 with one VCXO and a ...

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Appendix C The overall jitter transfer function also depends on the VCXO control voltage/frequency conversion ratio (Ko) parameter measured in radians per second per volt. In our PLL loop filter calculations, Ko equals approximately 400 for a VCXO with +/- ...

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... Phone: (91 11) 692 4780 Web Site www.conexant.com Fax: (91 11) 692 4712 World Headquarters Korea Phone: (82 2) 565 2880 Conexant Systems, Inc. Fax: (82 2) 565 1440 4311 Jamboree Road P. O. Box C Phone: (82 53) 745 2880 Newport Beach, CA Fax: (82 53) 745 1440 92658-8902 ...

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