RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 146

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

4.0 Registers
4.18 PRA Receive Write
PRA_EN
SYNCHR_EN
CRC4_MODE
A_MODE
AIS
RST_E_CNT
4-78
0xB1—PRA Receive Control Register 1 (RX_PRA_CTRL1)
RESET_CRC_CNT RESET_E_CNT
7
(reported also in TX_PRA_MON0), as follows:
NOTE:
The unused bit (bit 3) should be set to a value of 0.
Used to enable or globally disable the transmit PRA circuitry, as follows:
Used to enable or disable the PCM multiframe synchronization state machine, as follows:
Controls the behavior of the CRC bits transmitted towards the PCM link, as follows:
Controls the behavior of A-bits transmitted towards the PCM link, as follows:
Enables to override all 32 slots of an PCM frame except slot 0, transmitted towards the PCM
link with a constant pattern:
NOTE:
Clears the RX_E counter, as follows:
The Automatic mode operates in conjunction with the transmitter CRC4 check result
6
The value of this register takes effect starting with the next PCM multiframe
following the write access cycle completion.
AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern
generation, use the existing feature of the channel unit.
AIS
5
0 = Disable ALL TX PRA functionality
1 = Enable ALL TX PRA functionality
0 = Enable synchronization and force HUNT mode. Take RMSYNC as
indicator of frame.
1 = Disable synchronization. Take RMSYNC as multiframe indicator.
0 = Transparent
1 = From bits buffer 0
0 = Disable (Normal)
1 = 0xFF
AIS must be activated with reset_e_cnt = 1.
0 = Counter enabled
1 = Clear the E-receive counter
Receiver CRC Check
Code
00
01
10
11
A_MODE
Error
OK
4
Conexant
3
CRC4_MODE[1:0]
Re-calculated
Transparent
CRC4 Bits
E-bits Forced to:
Illegal
All 1
0
1
2
SYNCHR_EN
RS8953B/8953SPB
1
HDSL Channel Unit
N8953BDSB
PRA_EN
0