RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 44

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

3.0 Circuit Descriptions
3.2 PCM Channel
Figure 3-11. PCM Receive Sync Timing
3-12
PCM 6ms
RMSYNC
RMSYNC
RMSYNC
RMSYNC
RMSYNC
RMSYNC
RSER
Combination Table
3.2.2.1 Receive
3.2.2.2 Receive
Synchronization
0 1
RSER Bit 0, Frame 0
2
3 4
The Receive Multiframe Sync (RMSYNC) output can be programmed to mark
any bit position within the receive multiframe and does not affect RSER
alignment with respect to the PCM 6 ms frame.
offset between PCM 6 ms sync and RMSYNC for various bit and frame delay
values [RFRAME_LOC and RMF_LOC; addr 0xC3-C5]. The RS8953B does not
search receive data for T1, E1, or other specific framing patterns and must always
infer PCM receive frame timing from the master HDSL channel’s RSYNC
reference. When transmit PCM frames are synchronously mapped, the system can
program fixed receive delay values for RFRAME_LOC and RMF_LOC so that
RMSYNC marks the desired RSER bit position. For unframed or asynchronously
mapped applications, the RMSYNC output can be ignored, or the remote system
can measure transmit phase offset and communicate the necessary phase
displacement to the central site.
RSER data output for each PCM timeslot is supplied from one of seven data
sources via programmed assignments in the receive Combination Table
[COMBINE_TBL; addr 0xEE]. RSER can be supplied by payload bytes from one
of three HDSL receive channels, from fixed 8-bit patterns from one of three Data
Bank Registers [DBANK1–3; addr DC–DE] or from groomed Channel
Associated Signaling (CAS) from the Receive Signaling Table [RSIG_TBL; addr
0xF2]. The receive combination table contains up to 64 table entries
corresponding to RSER timeslot destinations and each table entry selects one of
seven data sources. The first PCM timeslot destination (counting from timeslot 0)
that selects a particular HDSL channel’s payload byte receives the first payload
byte mapped into the RFIFO from that particular HDSL channel’s payload block,
regardless of whether PCM is synchronously mapped. Asynchronously mapped
data is reconstructed into a serial PCM bit stream which maintains bit sequence
integrity, provided that the entire PCM channel is formed from combined payload
bytes. Each receive combination table entry also selects whether the associated
data is copied to the BER meter for test pattern examination.
RFRAME_LOC = 5, RMF_LOC = 0
RFRAME_LOC = 2, RMF_LOC = 0
RFRAME_LOC = 1, RMF_LOC = 0
Conexant
0
1
2 3
RSER Bit 0, Frame 1
4
RFRAME_LOC = 2, RMF_LOC = 1
RFRAME_LOC = 1, RMF_LOC = 1
RFRAME_LOC = 5, RMF_LOC = 1
Figure 3-11
RS8953B/8953SPB
shows the phase
HDSL Channel Unit
N8953BDSB