RS8953 Conexant Systems, Inc., RS8953 Datasheet
RS8953
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RS8953 Summary of contents
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... RS8953B/8953SPB HDSL Channel Unit The RS8953B is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit designed to perform data, clock, and format conversions necessary to construct a Pulse Code Multiplexed (PCM) channel from one, two, or three HDSL channels. The PCM channel consists of transmit and receive data, clock and frame sync signals configured for standard T1 (1544 kbps), standard E1 (2048 kbps), or custom (Nx64 kbps) formats ...
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... Plastic Leaded Chip Carrier (PLCC) RS8953SPB EPF 80–Pin Plastic Quad Flat Pack (PQFP) RS8953SPB EPJ 68–Pin Plastic Leaded Chip Carrier (PLCC) Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 HDSL Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 4.2 iv Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit 0x00—Transmit Embedded Operations Channel (TEOC_LO 5-10 0x01—Transmit Embedded Operations Channel (TEOC_HI 5-10 0x02—Transmit Indicator Bits (TIND_LO 5-10 0x03—Transmit Indicator Bits (TIND_HI 5-10 0x04— ...
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... Pattern (FILL_PATT 5-40 0xE4—Transmit Stuff Bit Value (TSTUFF 5-40 0xED—Transmit Routing Table (ROUTE_TBL 5-41 0xEE—Receive Combination Table (COMBINE_TBL 5-42 0xF2—Receive Signaling Table (RSIG_TBL 5-43 4.11 Common Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-44 0xE5—Command Register 1 (CMD_1 5-44 0xE6—Command Register 2 (CMD_2 5-45 vi Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit 0xE7—Command Register 3 (CMD_3 5-46 0xE8—Command Register 4 (CMD_4 5-47 0xE9—Command Register 5 (CMD_5 5-47 0xF3—Command Register 6 (CMD_6 5-48 0xF4—Command Register 7 (CMD_7 5-49 4.12 Interrupt and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 0xEB— ...
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... Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... A-1 Differences Between Bt8953A and RS8953B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A ...
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... Table of Contents x Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... Point-to-Multipoint (Fractional) System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Figure 1-7. Subscriber Modem (Terminal) System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Figure 1-8. RS8953B System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Figure 2-1. Three-Pair PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2-2. Single-Pair PLCC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 2-3 ...
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... RS8953B HDSL Channel Unit to Conexant HDSL Transceiver Interconnection . . . . . . . . . . 6-2 Figure 5-2. RS8953B HDSL Channel Unit to Bt8360 DS1 Framer Interconnection . . . . . . . . . . . . . . . . 6-3 Figure 5-3. RS8953B to 68302 Processor Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Figure 5-4. RS8953B HDSL Channel Unit to 8051 Controller Interconnection . . . . . . . . . . . . . . . . . . . 6-5 Figure 6-1. Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Figure 6-2 ...
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... RS8953B/8953SPB HDSL Channel Unit List of Tables Table 2-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Table 2-2. Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Table 3-1. PCM And HDSL Loopbacks 3-18 Table 3-2. HDSL Frame Structure and Overhead Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Table 3-3. HDSL Frame Mapping Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Table 3-4 ...
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... List of Tables xiv Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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HDSL Systems 1.1 HTU Applications The High-Bit-Rate Digital Subscriber Line (HDSL simultaneous full-duplex transmission scheme which uses twisted-pair wire cables as the physical medium to transport signals between standard types of network or subscriber communication interfaces. A ...
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... Code Multiplexed (PCM) channel of clock, serial data, and optional frame sync. ZipWire transceivers convert 2B1Q line signals to HDSL channels of clock, serial data, and quat sync. The RS8953B translates between PCM and HDSL by performing PCM timeslot and HDSL payload routing, data scrambling and descrambling, overhead insertion and extraction, clock synchronization and clock synthesis ...
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... Figure 1-3 channel bandwidth is transported over one or more HDSL wire pairs. The RS8953B provides drop/insert indicator signals to control external data MUXes and internal routing tables to map timeslots from either one of two synchronized PCM data sources. For remote terminals using partial payloads, the PCM channel may be configured to operate either at the standard interface rate or at the Nx64 effective payload rate ...
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... HDSL lines to transport Nx64 or standard T1/E1 applications. The RS8953B’s PCM timeslot router contains 64 table entries that extends the maximum PCM channel rate to 64x64 or 4.096 Mbps. RS8953B allows PCM channels at the central office (CO) and remote ends to operate at different rates ...
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... The RS8953B supplies the PCM frame sync reference and acts as the PCM bus master for the remote channel bank. The RS8953B’s Digital Phase Locked Loop (DPLL) clock recovery allows PCM channel rates down to 2x64 or 128 kpbs ...
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... PCM to HDSL frame syncs, each remote site can send its HDSL frames back to the central office. The HDSL frames are then sufficiently aligned with the others to be reconstructed into a single PCM frame at the central site. The RS8953B accommodates large differential delays associated with the P2MP application. It receives HDSL frame offsets to groom Channel Associated Signaling (CAS) from different sites ...
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... RS8953B/RS8953SPB HDSL Channel Unit 1.1.6 Subscriber Modem Figure 1-7 delivers PCM data directly to the RS8953B. Alternately, a multichannel communications controller such as the Bt8071A can be used to manage the transfer of data between the CPU and PCM channel through a local shared memory. Figure 1-7. Subscriber Modem (Terminal) System Block Diagram ...
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... HDSL Systems 1.2 System Interfaces 1.2 System Interfaces System interfaces and associated signals for the RS8953B functional circuit blocks are shown in and signals are defined in The single-pair version (RS8953SPBEPF and RS8953SPBEPJ) only supports HDSL Channel 1. HDSL Channels 2 and 3 are not usable. Although only 1 HDSL channel is usable, the internal registers are not changed from the 3 HDSL channel versions ...
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... Pin Descriptions 2.1 Pin Assignments The RS8953B pin assignments for the 68–pin Plastic Leaded Chip Carrier (PLCC) package are shown in assignments for the 80–pin Plastic Quad Flat Pack (PQFP) are shown in Figure 2-3 Table 2-1 coded as follows Input Output, I/O = Bidirectional, VCC = Power, GND = Ground, and Connection ...
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... Figure 2-1. Three-Pair PLCC Pin Assignments RDAT1 10 AD[0] 11 AD[1] 12 AD[2] 13 AD[3] 14 AD[4] 15 AD[5] 16 AD[6] 17 AD[7] 18 VCC 19 EXCLK 20 INSDAT 21 INSERT/RAUX2 22 INTR* 23 TMSYNC 24 RMSYNC 25 GND 26 2-2 60 TDAT3 59 SCLK MSYNC/RAUX3 58 57 TAUX3 TAUX2 56 55 TAUX1 TLOAD3 54 TLOAD2 53 RS8953BEPJ TLOAD1 52 WR* 51 ALE 50 VCC 49 PLLVCC 48 PLLDGND 47 PLLAGND 46 VEXT 45 VCC 44 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... INSDAT 21 (1) INSERT 22 INTR* 23 TMSYNC 24 RMSYNC 25 GND 26 NOTE(S): (1) These pins are only functional when RAUX_EN is not active (RAUX_EN = 0). N8953BDSB RS8953SPBEPJ Conexant 2.0 Pin Descriptions 2.1 Pin Assignments NC SCLK (1) MSYNC NC NC TAUX1 NC NC TLOAD1 WR* ALE VCC ...
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... GND 71 GND 72 BCLK2 TDAT2 75 RDAT2 76 GND 77 BCLK1 78 ROH1 79 TDAT1 2-4 RS8953BEPF Conexant RS8953B/8953SPB HDSL Channel Unit 40 MCLK CS DROP/RAUX1 36 GND 35 TMS TD0 32 TDI 31 TCK 30 RST* RD* 29 RSER 28 27 TSER 26 ...
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... GND 73 2 BCLK2 75 3 TDAT2 76 4 RDAT2 77 5 GND 78 6 BCLK1 79 7 ROH1 80 8 TDAT1 1 9 QCLK1 N8953BDSB RS8953SPBEPF I/O 80-Pin PQFP GND ( GND Conexant 2.0 Pin Descriptions 2 ...
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... RCLK 27 31 TSER 28 32 RSER RST TCK NOTE(S): (1) These pins do not perform the functions in RS8953SPBEPF and RS8953SPBEPJ. (2) These pins are only functional in RS8953SPBEPF and RS8953SPBEPJ when RAUX_EN is not active (RAUX_EN = 0). 2-6 68-Pin I/O 80-Pin PQFP I 32 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O ...
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... All MPU registers remain accessible while reset is active. Unless stated otherwise, reset activation does not affect the MPU register contents. RS8953B reset activation disables interrupts on the INTR* output by forcing all 1s in the Interrupt Mask Register (IMR), and zeros in the TX_ERR_EN, DPLL_ERR_EN, and RX_ERR_EN bits. ...
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... Z-bits. The last 40 Z-bits or any combination of payload bytes may be marked. O Indicate when overhead is received. Has two modes of operation: • RAS = 0. ROHn is high to mark only data passed into the RFIFO. • RAS=1. ROHn is high to mark only the last 40 Z-bits. Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Table 2-2. Signal Definitions ( Signal Name I/O TCLK Transmit Clock I RCLK Receive Clock EXCLK External Clock I TSER Transmit Serial I Data RSER Receive Serial Data TMSYNC Transmit I Multiframe Sync RMSYNC Receive Multiframe Sync MSYNC Transmit Master Sync N8953BDSB Description ...
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... Internal pull-ups (80-100 kW) are present on inputs to allow unused inputs to remain disconnected. (2) Internal pull-downs (80-100 kW) are present on inputs to allow unused inputs to remain disconnected. (3) The pins do not perform these functions in RS8953SPBEPF and RS8953SPBEPJ. 2-10 Description Drop/Insert O Active-high output indicates when specific PCM timeslots are present on RSER. ...
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... MHz. Systems that use 16 or 32-bit processors can add an external address buffer and data transceiver to connect the RS8953B. Faster bus speeds require external wait-state insertion logic. Figure 3-1. MPU Bus Control Logic ...
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... Interrupt Event Write ICR 3.1.1 Address/Data Bus Address/data bus pins AD[7:0] allow MPU access to RS8953B internal registers. Read and write access is allowed at any of the 256 address locations, but only defined register address locations are applicable (see 3.1.2 Bus Controls Five signals control register access: ALE, CS*, RD*, WR*, and MPUSEL. The address on AD[7:0] is latched on the falling edge of ALE, and CS active-low port enable for all read and write operations ...
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... Assertion of hardware reset (RST*) is required to preset all IMR bits, clear all error interrupt enables, and thus disable INTR* output. For backward compatibility with Bt8953 software, RST* also clears the command register bits added to RS8953B which aren’t present on prototype Bt8953. All other registers are MPU accessible while RST* is asserted. N8953BDSB ...
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... CH1 Transmit (Data and Sync) CH2 Transmit Transmit Formatter CH3 Transmit PCM 6 ms Sync Loopback (Data and Sync) CH1 Receive (Data and Sync) CH2 Receive Receive Formatter CH3 Receive Master Clock Sync DPLL Conexant RS8953B/8953SPB HDSL Channel Unit Figure 3-3 consists of Table 4-4) to define the number N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit 3.2.1 PCM Transmit The PCM transmit formatter shown in serial data on the TSER and INSDAT inputs. Both inputs are sampled on the clock edge selected by TCLK_SEL [CMD_2; addr 0xE6] according to the format of the PCM Multiframe Sync (MSYNC) output. The PCM transmit timebase outputs MSYNC to mark two clock cycles before the PCM input sample point of bit 0, frame 0. The timebase either references the system’ ...
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... Alignment of transmit PCM data in relation to MSYNC determines whether PCM Synchronization and HDSL frames are synchronously mapped. The RS8953B does not examine transmit data for T1, E1, or application framing patterns. Therefore, the system must apply PCM data aligned to MSYNC when synchronous mapping is desired. ...
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... PRBS pattern selections are: 2 where QRSS equals 2 inverter in the data path. RS8953B does not provide a mechanism to automatically insert logic errors in the test pattern, although the capability to synchronize and measure test pattern errors is provided by the BER meter. ...
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... PCM timeslots. The RS8953B provides DROP and INSERT signals to facilitate external multiplexing of individual timeslots from a shared PCM backplane, but does not provide the capability to three-state its data outputs during specific PCM timeslots. DROP and INSERT signals are programmed to mark RSER data output and INSDAT data input timeslots via the receive Combination Table [COMBINE_TBL ...
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... RS8953B/8953SPB HDSL Channel Unit 3.2.1.5 TFIFO Water Each HDSL transmit channel aligns the start of its output frame with respect to Levels the PCM 6 ms sync according to the programmed TFIFO water level values [TFIFO_WL; addr 0x05]. PCM 6 ms sync is created from MSYNC by the divisor programmed in MF_CNT [addr 0xC7] ...
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... RFIFO 3 Combine Table RX_RST PCM Receive Timebase Bit MF Frame MF Length Length Count RCLK_INV Conexant RS8953B/8953SPB HDSL Channel Unit constructs the serial data (RSER) Table 4-4). The PCM receiver Figure 3-10. PCM 6 ms Figure 3-13. FROM CH1 RMAP FROM CH2 RMAP FROM CH3 RMAP MASTER_SEL ...
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... RS8953B/8953SPB HDSL Channel Unit Figure 3-10. PCM Receive Data Timing HDSL 6ms Master RFIFO_WL = PCM Bit Delay PCM 6ms RMSYNC RSER 0 X Bit RSER Frame 0 Frame RSER Mframe 0 Mframe RMSYNC can mark any RSER bit position by programming RFAME_LOC and RMF_LOC. ...
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... PCM 6 ms frame. offset between PCM 6 ms sync and RMSYNC for various bit and frame delay values [RFRAME_LOC and RMF_LOC; addr 0xC3-C5]. The RS8953B does not search receive data for T1, E1, or other specific framing patterns and must always infer PCM receive frame timing from the master HDSL channel’ ...
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... RS8953B/8953SPB HDSL Channel Unit 3.2.2.3 BER Meter PCM timeslots from TSER or RSER can be examined for test patterns on a per timeslot-basis, or the entire framed or unframed PCM channel from TSER can be examined (see PRBS_MODE in CMD_3; addr 0xE7 and BER_SEL in CMD_6; addr 0xF3). When a test pattern is examined on a per timeslot-basis from receive ...
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... PCM 6ms Internal RSER CH1 selected as Master HDSL channel. NOTE(S): 3-14 Z1 byte1 to RFIFO1 Z byte1 to RFIFO2 16-bit SYNC + HOH Z byte1 to RFIFO3 RFIFO_WL = PCM Bit Delay RSER Bit 0, Frame 0 Conexant RS8953B/8953SPB HDSL Channel Unit Figure 3-13. RFIFO_WL selects the byte2 byte2 byte2 N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit 3.3 Clock Recovery DPLL The Digital Phase Locked Loop (DPLL) shown in PCM Receive Clock (RCLK) from a 60–80 MHz High Frequency Clock (HFCLK). HFCLK is developed by analog PLL multiplication of the MCLK input frequency, or HFCLK is applied directly to the MCLK input (see PLL_MUL and PLL_DIS in CMD_1 ...
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... HFCLK accuracy ( 20 ppm) and programmed scale factor accuracy (~ 2 Hz). Open loop operation is useful during remote HTU applications to provide a stable RCLK output frequency while HDSL channels are performing startup activities. 3-16 511 GCLK cycles according to the initialization mode Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... When performing PH_LOOP, all HDSL channels that have payload data mapped require that PH_LOOP mode be enabled to complete PCM channel loopback on the HDSL side. Also, the same tap must be used for the RS8953B scrambler and descrambler, or both the RS8953B scrambler and descrambler must be disabled ...
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... Transmit HDSL Loopback on PCM Side Receive PCM Loopback on HDSL Channel 1 Receive PCM Loopback on HDSL Channel 2 Receive PCM Loopback on HDSL Channel 3 Transmit HDSL Loopback on HDSL Channel 1 Transmit HDSL Loopback on HDSL Channel 2 Transmit HDSL Loopback on HDSL Channel 3 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit 3.5 HDSL Channel The three identical HDSL channels (CH1, CH2, and CH3) consist of separate transmit and receive circuits that are responsible for the assembly of HDSL output frames and the disassembly of HDSL receive frames. The basic structure of an HDSL frame is shown in consists of 48 payload blocks with each block containing a single Z-bit, plus an application-specific number of payload bytes ...
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... Unspecified Indicator Bit Payload Blocks 37–48 47 sq1 Stuff Quat Sign 48 sq2 Stuff Quat Magnitude 49 sq3 Stuff Quat Sign 50 sq4 Stuff Quat Magnitude Conexant RS8953B/8953SPB HDSL Channel Unit HOH Register Bit — IND[0] IND[1] EOC[0]–EOC[3] — IND[2] IND[3] IND[4] EOC[4] EOC[5]–EOC[8] — ...
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... RS8953B/8953SPB HDSL Channel Unit In T1 framing mode [E1_MODE = 0 in CMD_1; addr 0xE5], Z-bit positions are replaced by F-bits and are treated as payload with respect to the PCM channel. Figure 3-16 payload block contains 1 F-bit, plus 12 payload bytes. The figure also illustrates F-bits routed as payload to both HDSL channels and demonstrates the order in which PCM timeslots are routed to payload bytes: bytes 1 through 12 correspond to PCM timeslots 1– ...
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... BYTE BYTE BYTE BYTE 8- BITS BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE B NN 97/784 MS Conexant RS8953B/8953SPB HDSL Channel Unit 5 870 0 YNC ORD “ ...
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... RS8953B/8953SPB HDSL Channel Unit Table 3-3. HDSL Frame Mapping Examples Payload BYTE1 BYTE2 BYTE 3–35 BYTE36 BYTE37 BYTE 38–71 BYTE 72 BYTE 73–107 BYTE108 BYTE109–143 BYTE 144 N8953BDSB 2E1 VC- BYTES 32 BYTES 0000 RR 32 BYTES 32 BYTES ...
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... EOC Scrambler Stuff Generator CMP Stop Start Threshold CNT GCLK 4-2) and TSTUFF [addr 0xE4] register values. CRC bits are calculated Conexant RS8953B/8953SPB HDSL Channel Unit RDATn QCLKn 2B1Q TDATn Align HH_LOOP = Command Register Bit Table 3-2 for HOH bit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit 3.5.1.3 CRC Calculation The Cyclic Redundancy Check (CRC) calculation is performed on all transmit data, and the HOH multiplexer inserts the resulting 6-bit CRC into the subsequent output frame. CRC is calculated over all bits in the (N)th frame except the SYNC, STUFF, and CRC bits, and then is inserted into the (N+1)th frame. The MPU can choose to inject CRC errors on a per frame-basis by setting ICRC_ERR [TCMD_1 ...
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... Conexant RS8953B/8953SPB HDSL Channel Unit Table 3-4 for Quaternary Symbol (Quat –1 –3 Comments Pair Identification Pair Identification Pair Identification Not defined Not defined Not defined Not defined Not defined Not defined ...
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... RS8953B/8953SPB HDSL Channel Unit 3.5.1.7 HDSL Auxiliary The HDSL auxiliary transmit channel provides an alternate source of HDSL Transmit payload bytes and optionally, an alternate source for the last 40 Z-bits transmitted in each HDSL frame. Auxiliary transmit data (TAUXn) is sampled by BCLKn whenever TLOADn is active-high, as shown in is enabled by TAUX_EN [TCMD_2; addr 0x07] and programmed in the Transmit Payload Map Registers [TMAP ...
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... Circuit Descriptions 3.5 HDSL Channel 3.5.2 HDSL Receive The RS8953B contains three identical HDSL receivers, each receiver the same as the one shown in destuffing, overhead extraction, descrambling of payload data, error performance monitoring, and payload mapping of HDSL data from received frames into the RFIFO. The receive framer monitors incoming HDSL data to locate SYNC words ...
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... RS8953B/8953SPB HDSL Channel Unit 3.5.2.2 HDSL Receive The HDSL receive framer acquires and maintains synchronization of the HDSL Framer channel and generates pointers that control overhead extraction in the STUFF, CRC and HOH demux circuitry. The MPU initializes the framer to the Out Of Sync state by writing any data value to SYNC_RST [addr 0x63]. From the Out Of Sync state, the framer advances to Sync Acquired when a correct SYNC word is detected ...
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... Figure 3-23. HDSL Receive Framer Synchronization Consecutive SYNC_ACQUIRED States per REACH_SYNC Criteria 1 SYNC No SYNC OUT_OF SYNC No SYNC No SYNC 8 Consecutive SYNC_ERRORED States per LOSS_SYNC Criteria 3-30 Figure 3-23 Conexant RS8953B/8953SPB HDSL Channel Unit 7 8 SYNC SYNC IN_SYNC SYNC No SYNC 2 1 N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit After entering In Sync, the framer either remains In Sync as successive sync words are detected, or regresses to the Sync Errored state if sync pattern errors are found. During Sync Errored states, the number of matching bits from each comparison of received sync word and programmed sync word patterns must meet or exceed the programmed pattern match tolerance specified by THRESH_CORR [RCMD_2 ...
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... Table 3-2 4-10). The MPU must read the contents of the HOH registers every 6 ms, or 3-25, or marks only the last 40 Z-bits, as shown 14-bit SYNC Conexant RS8953B/8953SPB HDSL Channel Unit for HOH bit positions within the Figure 3-26. The RAUX_EN = 1 RAZ = 0 IND Z1 byte1 ...
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... RS8953B/8953SPB HDSL Channel Unit Figure 3-26. HDSL Auxiliary Receive Z-bit Timing Payload Blocks ROH BCLK EOC0-3, CRC1-2, IND2-4, EOC4 RAUX ROH N8953BDSB Z13 Block 13, byte1 Conexant 3.0 Circuit Descriptions 3.5 HDSL Channel RAUX_EN = 1 RAZ = 1 Block 13, byte2 3-33 ...
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... CPU. The counter is reset upon reading the value. 3-34 Figure 3-27 shows an overview of the HDSL link between the RS8953B RS8953B HDSL E-bits E-bits E-bits E-bits Conexant RS8953B/8953SPB HDSL Channel Unit TSER TMSYNC ET RESER RMSYNC N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Enabling the CRC4 generator causes CRC4 regeneration of the E1 data (RSER). The result is inserted into the data stream in the appropriate location in accordance with the CRC4 procedure specified in CCITT recommendation G.704. If the CRC4 generator is disabled, the following options are available: New values are inserted for the CRC4 bits, or you can leave the CRC4 bits untouched ...
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... Selecting transparent or non-transparent affects all the FAS bits. For non-transparent bits, the FAS value is inserted into the correct location of the data stream (TSER). The FAS is a constant pattern. Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... Registers All RS8953B registers are read-only or write-only. For registers that contain less than 8 bits, assigned bits reside in LSB positions; unassigned bits are ignored during write cycles and are indeterminate during read cycles. The LSB in all registers is bit position 0. All registers are randomly accessible except for the 64 ...
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... The MPU writes to non-real time command registers which are event-driven and which are written when the system initializes, changes modes, or responds to an error condition. Whenever data is written to a RS8953B register, the data is first written to the Shadow Write Register [SHADOW_WR; addr 0x3B], and then the data is transferred from the SHADOW_WR register to the addressed register ...
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... RS8953B/8953SPB HDSL Channel Unit 4.1 Address Map The channel column (CHn) of Table 4-1 each register. Common registers are indicated by a ‘C’ in the CHn column. Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0x00 1 TEOC_LO 0x01 1 TEOC_HI 0x02 1 TIND_LO 0x03 1 TIND_HI ...
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... FEBE_CNT — — — — C PHS_ERR — C MSYNC_PHS_LO — C MSYNC_PHS_HI — C SHADOW_WR — C ERR_STATUS — — — 4-10 C TX_PRA_CTRL0 4-10 C TX_PRA_CTRL_1 4-10 C TX_PRA_MON1 4-10 C TX_PRA_E_CNT Conexant RS8953B/8953SPB HDSL Channel Unit Page Ref. 4-55 4-60 4-61 4-61 4-62 4-58 4-59 — — — — — 4-62 4-59 4-59 — — — — — 4-62 4-59 4-59 — 4-63 4-63 4-63 4-64 4-64 — 4-65 4-66 4-67 4-67 N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0x44 3 TZBIT_1 0x45 3 TFIFO_WL 0x46 3 TCMD_1 0x47 3 TCMD_2 0x48 3 TMAP_1 0x49 3 TMAP_2 0x4A 3 TMAP_3 0x4B 3 TMAP_4 0x4C 3 TMAP_5 0x4D 3 TFIFO_RST 0x4E 3 SCR_RST 0x4F 3 TMAP_6 0x50 3 TMAP_7 0x51 ...
Page 74
... Conexant RS8953B/8953SPB HDSL Channel Unit Page Ref. 4-75 4-75 4-75 4-76 4-76 4-76 — — — — — — — — — — — — — — — — — ...
Page 75
... RS8953B/8953SPB HDSL Channel Unit Table 4-1. Register Summary Address Map ( Addr CHn Write Register 0xC8 C FRAME_LEN_LO 0xC9 C FRAME_LEN_HI 0xCA C HFRAME_LEN_LO 0xCB C SYNC_WORD_A 0xCC C SYNC_WORD_B 0xCD C RFIFO_WL_LO 0xCE C RFIFO_WL_HI 0xCF C STF_THRESH_A_LO 0xD0 C STF_THRESH_A_HI 0xD1 C STF_THRESH_B_LO 0xD2 C STF_THRESH_B_HI 0xD3 C STF_THRESH_C_LO 0xD4 C STF_THRESH_C_HI 0xD5 ...
Page 76
... Conexant RS8953B/8953SPB HDSL Channel Unit Page Ref. — — — — — — — — — — — — — — — — N8953BDSB ...
Page 77
... RS8953B/8953SPB HDSL Channel Unit 4.2 HDSL Transmit HDSL Channel 1 Base Address Table 4-2. HDSL Transmit Write Registers CH1 CH2 CH3 0x00 0x20 0x40 0x01 0x21 0x41 0x02 0x22 0x42 0x03 0x23 0x43 0x04 0x24 0x44 0xDF 0xE0 0xE1 0xE2 0xE3 0x05 0x25 0x45 ...
Page 78
... TIND coincident with the respective HDSL channel’s transmit 6 ms frame interrupt. Unmodified registers repeatedly output their contents in each frame. TIND[0] is transmitted first. The RS8953B does not automatically output FEBE. Proper transmit of FEBE requires NOTE: the MPU to copy the CRC_ERR bit from STATUS_2 [addr 0x06] to TIND[1]. ...
Page 79
... RS8953B/8953SPB HDSL Channel Unit 0xDF—Transmit Z-Bits (TZBIT_2 0xE0—Transmit Z-Bits (TZBIT_3 0xE1—Transmit Z-Bits (TZBIT_4 0xE2—Transmit Z-Bits (TZBIT_5 0xE3—Transmit Z-Bits (TZBIT_6 Transmit Z-bits is applicable only in E1_MODE [CMD_1; addr 0xE5]; otherwise, Z-bit TZBIT[47:0] registers are ignored. TZBIT[47:0] holds 48 Z-bits for transmission in the first bit of each of the 48 payload blocks ...
Page 80
... SYNC_WORD_B [addresses 0xCB–0xCC], for transmission in the next frame. 4- TFIFO_WL[7: HOH_EN SYNC_SEL 0 = Scrambler bypassed 1 = Scrambler enabled 0 = Four-level 2B1Q encoder operation 1 = Two-level 2B1Q encoder operation 0 = Normal CRC transmission 1 = Transmit errored CRC 0 = SYNC_WORD_A is transmitted 1 = SYNC_WORD_B is transmitted Conexant RS8953B/8953SPB HDSL Channel Unit ICRC_ERR TWO_LEVEL SCR_EN N8953BDSB ...
Page 81
... RS8953B/8953SPB HDSL Channel Unit HDSL Overhead Enable—The HOH multiplexer inserts EOC, IND, and CRC bits. Otherwise, HOH_EN transmit overhead bits, except SYNC and STUFF, are forced to all 1s. HOH_EN = 0 select transmission of two-level or four-level scrambled 1s. Force All 1s Payload—Transmit payload data bytes are replaced by all 1s. FORCE_ONE and FORCE_ONE HOH_EN are both set to enable output of a four-level framed, scrambled-1s signal ...
Page 82
... Normal transmit 1 = Cross-connect CH1 and CH2 0 = Last 40 Z-bits supplied by TZBIT2–TZBIT6 registers 1 = Last 40 Z-bits supplied by TAUXn 0 = Increased wander and decreased jitter (in any register Decreased wander and increased jitter (in all three registers) Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
Page 83
... PCM timeslots, DBANK registers, or the HDSL auxiliary channel data. All routed timeslots to a given channel’s TFIFO must also be mapped out of the TFIFO. The RS8953B sequentially maps payload and cannot rearrange byte ordering but allows payload from the DBANK registers to be interleaved with PCM data ...
Page 84
... DBANK_3 is active and TAUXn supplies data during selected payload byte. 2. When DBANK_3, TAUX_EN and EXT_ZBIT [TCMD_2; addr 0x07] are selected, TLOADn output is active and TAUXn supplies data during the last 40 Z-bits. Conexant RS8953B/8953SPB HDSL Channel Unit BYTE21 TMAP[1: ...
Page 85
... Payload Map [TMAP; addr 0x08], or the PCM Routing Table [ROUTE_TBL; addr 0xED] each time PCM MultiFrame Sync (TMSYNC) experiences a change of frame alignment and whenever the TFIFO reports an overflow, underflow, or slip error. The RS8953B asserts TFIFO_RST automatically whenever a transmit STUFF error is detected. ...
Page 86
... Bits 8 8 – – – 4 Receive Signaling Location Conexant RS8953B/8953SPB HDSL Channel Unit HDSL Channel 3 (CH3) 0xA0 Name/Description Configuration Configuration Receive FIFO Reset Receive Framer Reset Payload Map Payload Map Payload Map Payload Map Payload Map Payload Map ...
Page 87
... RS8953B/8953SPB HDSL Channel Unit 0x60—Receive Command Register 1 (RCMD_1 FRAMER_EN[1:0] Reach Sync Framing Criteria—Contains the number of consecutive HDSL frames in which REACH_SYNC[2:0] the SYNC word is detected before the receive framer moves from the OUT_OF_SYNC to the IN_SYNC state. REACH_SYNC determines the number of SYNC_ACQUIRED intermediate states the framer must pass through during recovery of frame sync ...
Page 88
... HTU-C or LTU terminal type, descrambler selects tap HTU-R or NTU terminal type, descrambler selects tap Descrambler bypassed 1 = Descrambler enabled 0 = Normal receive 1 = RDATn supplied by TDATn Conexant RS8953B/8953SPB HDSL Channel Unit THRESH_CORR[3:0} SYNC Threshold Correlation 10 or more out of 14 bits ...
Page 89
... RS8953B/8953SPB HDSL Channel Unit Receive Error Interrupt Enable—Receive errors request RX_ERR interrupt and report RX_ERR_EN RXn_ERR status upon detection of RFIFO errors [STATUS_1; addr 0x05], framer state transitions or error counter overflows [STATUS_2; addr 0x06]. Disabled channels are prevented from activating INTR*, or setting RX_ERR [IRR; addr 0x1F]. Receive errors are always latched in ERR_STATUS [addr 0x3C] regardless of RX_ERR_EN. 0x62— ...
Page 90
... Payload Map (RMAP_3 — — 0x69—Receive Payload Map (RMAP_4 — — 0x6A—Receive Payload Map (RMAP_5 — — 4- RMAP[5: RMAP[11: RMAP[17:12 RMAP[23:18 RMAP[29:24] Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
Page 91
... RS8953B/8953SPB HDSL Channel Unit 0x6B—Receive Payload Map (RMAP_6 — — Receive Payload Map—Six registers hold a 36-bit value to define which of the received HDSL RMAP[35:0] payload bytes (byte1 through byte36) are placed into the RFIFO. RMAP[0] corresponds to the first HDSL payload byte (byte1 mode, F-bits are mapped by enabling one extra byte after the last payload mapped byte ...
Page 92
... NOTE: capability may be used by the NTU to transfer the results of the RMSYNC phase measurement back to the LTU. Remote sites must align HDSL transmit frames to their respective PCM Transmit Multiframe Sync (TMSYNC) for this equation to remain valid. 4-24 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
Page 93
... Programmed frame and multiframe lengths for both timebases allows the RS8953B to continue operating at appropriate intervals when PCM transmit sync or HDSL receive sync references are lost, and when RS8953B acts as the PCM bus master. The transmit timebase controls the routing of PCM timeslots into the transmit FIFOs, while the receive timebase controls the extraction of PCM timeslots out of the receive FIFOs ...
Page 94
... TFRAME_LOC[8:0] = Decimal (hex 256 bits T1 = 193 bits 64x64 = 512 bits TMF_LOC[5] PCM Multiframe Length TMF_LOC[5:0] = Decimal (hex frames frames ESF = 24 frames Conexant RS8953B/8953SPB HDSL Channel Unit — TFRAME_LOC[8] 253 (0x0FD) 190 (0x0BE) 509 (0x1FD (0x0E) ...
Page 95
... RS8953B/8953SPB HDSL Channel Unit 0xC4—RSER Frame Bit Location (RFRAME_LOC_HI — — — RSER Frame Bit Location—Establishes the number of PCM bit delays, in the range of 1 bit to RFRAME_LOC[8:0] 512 bits, from the internal PCM receive timebase’s output of bit 0 to the rising edge of RMSYNC ...
Page 96
... HDSL frame. MF_CNT operates in conjunction with FRAME_LEN and MF_LEN to create transmit and receive PCM 6 ms timebases which are needed to perform transmit bit stuffing and DPLL receive clock recovery. The RS8953B requires the product of MF_LEN and MF_CNT to always equal 48 to match the number of HDSL payload blocks in an HDSL frame. For example: 0xC8— ...
Page 97
... RS8953B/8953SPB HDSL Channel Unit 4.7 HDSL Channel Configuration Table 4-5. HDSL Channel Configuration Write Registers Address Register Label 0xCA HFRAME_LEN_LO 0xF5 HFRAME_LEN_HI 0xF8 HFRAME2_LEN_LO 0xF9 HFRAME2_LEN_HI 0xFA HFRAME3_LEN_LO 0XFB HFRAME3_LEN_HI 0xCB SYNC_WORD_A 0xCC SYNC_WORD_B 0xCD RFIFO_WL_LO 0xCE RFIFO_WL_HI 0xCF STF_THRESH_A_LO 0xD0 STF_THRESH_A_HI 0xD1 ...
Page 98
... HFRAME_LEN[8:0] that are transmitted and received in an HDSL payload block. Each payload block is comprised of an integer number of 8-bit bytes plus an additional F-bit or Z-bit. The RS8953B repeats the payload block length 48 times to form one HDSL frame. A value of 15 selects a 16-bit payload block length; therefore, the programmed value of HFRAME_LEN equals eight times the number of payload bytes ...
Page 99
... RS8953B/8953SPB HDSL Channel Unit 0xFB—HDSL Frame Length (HFRAME3_LEN_HI — — — HDSL Payload Block Length—Contains the number of BCLK3 bits, in the range 512, HFRAME3_LEN[8:0] that are transmitted and received in an HDSL payload block for Channel 3. In theory, the HDSL frame length can be different for each loop. But if the HDSL frame lengths are not close to the same value, RFIFO errors will probably occur ...
Page 100
... HDSL bits worth of phase at the BCLKn frequency (f equation: 4- — — < STF_THRESH_A STF_THRESH_A < STF_THRESH_C STF_THRESH_C n f MCLK ------------------------ - StuffingThreshold = f HDSL Conexant RS8953B/8953SPB HDSL Channel Unit — RFIFO_WL[9:8] ), PLL Multiplication MCLK Inserted STUFF Bits ( shown in the following HDSL PLL_MUL -------------------------- - PLL_DIV ...
Page 101
... RS8953B/8953SPB HDSL Channel Unit where for STF_THRESH_A 0xCF—Bit Stuffing Threshold A (STF_THRESH_A_LO 0xD0—Bit Stuffing Threshold A (STF_THRESH_A_HI — — — Bit Stuffing Threshold A—Contains the number of GCLK cycles equaling 8 HDSL bit times. STF_THRESH_A[8:0] If the phase measured from PCM to HDSL 6 ms frames is a positive value greater than or equal to STF_THRESH_A, then 4 STUFF bits are inserted in the outgoing HDSL frame ...
Page 102
... PCM, or GCLK inputs is exceeded and the STUFF generator reports STUFF_ERR [STATUS_3; addr 0x07]. STF_THRESH_C must be greater than STF_THRESH_B by a value of 4 HDSL bit NOTE: times (4 x HDSL 4- — — — GCLK) but not greater than a value of 0x3FF. Conexant RS8953B/8953SPB HDSL Channel Unit 1 0 STF_THRESH_C[9:8] N8953BDSB ...
Page 103
... N8953BDSB Bits Name/Description 8 DPLL Residual 8 DPLL Residual 8 DPLL Factor 7 DPLL Gain 8 DPLL Phase Detector Init (optional for RS8953B) — DPLL Phase Detector Reset f MCLK ------------------------------------------------ - [INTEGER.FRACTION MCLK input frequency MCLK f = RCLK output frequency desired PCM INTEGER = Integer part of result [DPLL_FACTOR; addr 0xD7] FRACTION = Fractional part of result [DPLL_RESID ...
Page 104
... DPLL_FACTOR = 257 INTEGER – = Round to nearest integer FRACTION = Fraction from INTEGER.FRACTION calculation INTEGER = Integer from INTEGER.FRACTION calculation PLL_MUL PLL_DIV DPLL_FACTOR DPLL_FACTOR[7:0] Conexant RS8953B/8953SPB HDSL Channel Unit 65535 DPLL_RESID 0xEB 0x578B 0xF1 0xD7FF 0xEF 0x4000 N8953BDSB ...
Page 105
... Conexant 4.0 Registers 4.9 DPLL Configuration DC_INTEG[3:0] RS8953B RS8953B –4 2 –3 2 –2 2 – (Type I) 4-37 ...
Page 106
... When MPU supplied, DPLL_PINI sets the initial point within the phase comparator window that the phase detector returns to after detection of a DPLL error. The RS8953B phase window is 1,024 GCLK cycles. For example, the RS8953B requires a programmed value for DPLL_PINI which is typically set to init phase window at its center point (i ...
Page 107
... RS8953B/8953SPB HDSL Channel Unit 4.10 Data Path Options Table 4-7. Data Path Options Write Registers Address Register Label 0xDC DBANK_1 0xDD DBANK_2 0xDE DBANK_3 0xEA FILL_PATT 0xE4 TSTUFF 0xED ROUTE_TBL 0xEE COMBINE_TBL 0xF2 RSIG_TBL 0xDC—Data Bank Pattern 1 (DBANK_1 Data Bank Pattern 1—Holds an 8-bit programmable pattern that can be used to replace ...
Page 108
... HDSL output frame contains bit stuffing. TSTUFF[0] is the sign bit and first bit of the first quat transmitted during STUFF words. 4- DBANK_3[7: FILL_PATT[7: — TSTUFF[3:0] MAG1 SIGN1 Conexant RS8953B/8953SPB HDSL Channel Unit MAG0 SIGNO N8953BDSB ...
Page 109
... MPU access to the transmit routing table’s single (ROUTE_TBL) register is enabled by first setting ROUTE_EN [CMD_3; addr 0xE7] to reset the table pointer. The MPU can then write table entries sequentially to the ROUTE_TBL address. The RS8953B increments the internal table pointer after each write to ROUTE_TBL. ...
Page 110
... HDSL receive channel 2 11 HDSL receive channel BER Meter ignores PCM timeslot 1 = BER Meter receives copy of PCM timeslot data from RSER 0 = DROP output pin remains inactive (low DROP output pin active (high) Conexant RS8953B/8953SPB HDSL Channel Unit BER_EN COMBINE[1:0] N8953BDSB ...
Page 111
... HDSL channel supplies the CAS Multiframe Alignment Signal (MAS) and which channel supplies the extra and multiframe yellow alarm bits (XYXX). RS8953B does not provide access to the actual received TS16 data and assumes that EOC messages or indicator bits are used to report far-end alarm and status information. ...
Page 112
... HFCLK Divisor Normal PLL operation 1 = Disable PLL (PLL_MUL value has no effect HDSL payload includes F-bits (T1 mode HDSL payload includes Z-bits (E1 mode) Conexant RS8953B/8953SPB HDSL Channel Unit Configuration Configuration Configuration Configuration Configuration Configuration Configuration PLL_MUL[3: ...
Page 113
... RS8953B/8953SPB HDSL Channel Unit 0xE6—Command Register 2 (CMD_2 GCLK_SEL PCM_FLOAT HP_LOOP PCM Transmit Clock Source—Selects which clock source and clock edge are used for PCM TCLK_SEL transmit inputs and outputs. PCM Receive Clock Source—Selects which clock source and which clock edge is used for RCLK_SEL PCM receive outputs. See also RCLK_INV [CMD_7 ...
Page 114
... Test Pattern (14-zero limit Disable access to RSIG_TBL 1 = Enable MPU access to RSIG_TBL and reset write pointer Conexant RS8953B/8953SPB HDSL Channel Unit PRBS_DIS ROUTE_EN COMB_EN Approximate Scale LFSR Tap Selection ...
Page 115
... RS8953B/8953SPB HDSL Channel Unit 0xE8—Command Register 4 (CMD_4) Must be set to 0x04 before any other MPU access to device, for normal operation. Other values are reserved for Conexant production test. 0xE9—Command Register 5 (CMD_5 DPLL_NCO MASTER_SEL[1:0] Master STUFF source is applicable only if SLV_STUF [TCMD_2; addr 0x07] is enabled. The STUFF_SEL[1:0] slave’ ...
Page 116
... TMSYNC to MSYNC phase measurement 1 = RMSYNC to MSYNC phase measurement 0 = Normal receive 1 = Enable receive signaling table 0 = DROP, INSERT, or MSYNC outputs enabled 1 = RAUXn outputs enabled 0 = ROHn marks all non-payload data 1 = ROHn marks only the last 40 Z-bits Conexant RS8953B/8953SPB HDSL Channel Unit BER_SEL[1:0] Mode Description N8953BDSB ...
Page 117
... RS8953B/8953SPB HDSL Channel Unit 0xF4—Command Register 7 (CMD_7 PRA_EN FEBE_POLARITY NCO_SCALE DPLL Error Interrupt Enable—Enables DPLL errors to request RX_ERR interrupt when an DPLL_ERR_EN overflow or underflow condition occurs at the phase detector output. DPLL errors are latched and reported in ERR_STATUS [addr 0x3C] regardless of DPLL_ERR_EN. ...
Page 118
... Normal NCO operation 1 = Divide NCO clock (HFCLK MCLK ------------------------------------------------ - [INTEGER.FRACTION FEBE counter increments when FEBE bit is high 1 = FEBE counter increments when FEBE bit is low 0 = Disable ALL PRA functionality 1 = Enable ALL PRA functionality Conexant RS8953B/8953SPB HDSL Channel Unit PLL_MUL 2 f PCM N8953BDSB ...
Page 119
... RS8953B/8953SPB HDSL Channel Unit 4.12 Interrupt and Reset Table 4-9. Interrupt and Reset Write Registers Address Register Label 0xEB IMR 0xEC ICR 0xEF BER_RST 0xF0 PRBS_RST 0xF1 RX_RST 0xEB—Interrupt Mask Register (IMR) The MPU writes IMR bit to mask the respective interrupt event. Masked interrupt sources are prevented from generating an active low signal on the INTR* output, but are reported in the Interrupt Request Register (IRR) ...
Page 120
... Receiver (RX_RST) For the RS8953B, writing any data value to RX_RST forces the PCM formatter to align the PCM receive timebase with respect to the master HDSL channel’s receive 6 ms frame by reloading the RFIFO_WL value [addr 0xCD]. The MPU must write RX_RST after modifying the RFIFO_WL value in the RS8953B. The RS8953B automatically performs RX_RST each time the master HDSL channel’ ...
Page 121
... RS8953B/8953SPB HDSL Channel Unit 4.13 Receive/Transmit Status HDSL Channel 1 (CH1) Base Address Table 4-10. Receive and Transmit Status Read Registers CH1 CH2 CH3 Register Label 0x00 0x08 0x10 REOC_LO 0x01 0x09 0x11 REOC_HI 0x02 0x0A 0x12 RIND_LO 0x03 0x0B 0x13 RIND_HI 0x04 0x0C ...
Page 122
... CH3 (address 0x13) 0x04—Receive Z-Bits (RZBIT_1 4- RE0C[12:8] 001 010 100 RIND[7: RIND[12:8] Rev A Rev B 000 000 010 010 000 001 RZBIT[7:0] Conexant RS8953B/8953SPB HDSL Channel Unit Rev C 000 010 010 1 0 N8953BDSB ...
Page 123
... RS8953B/8953SPB HDSL Channel Unit 0x18—Receive Z-Bits (RZBIT_2 0x19—Receive Z-Bits (RZBIT_3 0x1A—Receive Z-Bits (RZBIT_4 0x1B—Receive Z-Bits (RZBIT_5 0x1C—Receive Z-Bits (RZBIT_6 Receive Z-bits—Applicable only in E1_MODE [CMD_1; addr 0xE5]. RZBIT holds 48 Z–bits RZBIT[47:0] received during the previous HDSL frame ...
Page 124
... Tip/Ring Inversion—Indicates the receive framer acquired an inverted SYNC word TR_INVERT indicating that the receive tip and ring wire pair connections are reversed. The RS8953B automatically inverts the sign bits of all received data presented on the RDATn input when inversion is detected. TR_INVERT is updated each time the receive framer state transitions from OUT_OF_SYNC to SYNC_ACQUIRED. Receive STUFF— ...
Page 125
... RS8953B/8953SPB HDSL Channel Unit 0x06—Receive Status 2 (STATUS_2 FEBE_OVR CRC_OVR CRC_ERR Intermediate State Count—Applicable only if SYNC_STATE reports SYNC_ACQUIRED or STATE_CNT[2:0] SYNC_ERRORED states. STATE_CNT indicates the framer’s progress through the intermediate states. Receive Framer Synchronization State—Reports the state of the receive framer. Refer to the ...
Page 126
... TFIFO_MPTY STUFF bits output STUFF bits output 0 = TFIFO normal 1 = TFIFO overflowed 0 = TFIFO normal 1 = TFIFO Underrun 0 = Transmit FIFO normal 1 = Transmit FIFO unbalanced 0 = STUFF generator normal 1 = STUFF generator error 4 3 CRC_CNT[7:0] Conexant RS8953B/8953SPB HDSL Channel Unit TFIFO_FULL TX_STUFF N8953BDSB ...
Page 127
... RS8953B/8953SPB HDSL Channel Unit CRC Error Count—Indicates the total number of received CRC errors detected by the receive CRC_CNT[7:0] framer, and increments by one for each received HDSL 6 ms frame that contains CRC_ERR [STATUS_1; addr 0x06]. CRC_CNT is cleared ERR_RST [addr 0x67]. Error counting is suspended while the receive framer is OUT_OF_SYNC or SYNC_ACQUIRED. CRC_CNT also sets CRC_OVR [STATUS_2 ...
Page 128
... DPLL Residual 8 DPLL Residual 8 Interrupt Mask Register 8 DPLL Phase Error 8 Multiframe Sync Phase 5 Multiframe Sync Phase 8 Shadow Write BER[7:0] BER_SCALE Conexant RS8953B/8953SPB HDSL Channel Unit Error Status Bit Error Ratio 31 BER[7: BER[7: BER[7: BER[7:0] 2 N8953BDSB ...
Page 129
... RS8953B/8953SPB HDSL Channel Unit 0x1E—BER Status (BER_STATUS — — — BER Pattern SYNC—Applicable only if SYNC_DONE is active. BER_SYNC reports BER_SYNC whether the BER meter acquired test pattern sync during the 128-bit test pattern qualification period. The BER meter must detect fewer than 8 bit errors during examination of the first 128 bits to assert BER_SYNC ...
Page 130
... IMR read value to mask read data from the IRR and to avoid processing of masked interrupts. 4-62 Table 4-10) and the DPLL status of the master HDSL receive 4-11 interrupt 1 = Receive frame interrupt interrupt 1 = Transmit error interrupt interrupt 1 = Receive error interrupt 4 3 RESID_OUT[7: RESID_OUT[15:8] Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
Page 131
... RS8953B/8953SPB HDSL Channel Unit 0x38—DPLL Phase Error (PHS_ERR DPLL Phase Error—The DPLL phase detector error output is given in 2’s complement format PHS_ERR[7:0] in units of GCLK cycles, where minimum (negative) phase is reported as 0x80 and maximum (positive) phase as 0x7F. The result of the PCM to HDSL 6 ms phase comparison is updated coincident with the RXn interrupt (where n = master HDSL channel number). During DPLL closed loop operation, the phase error’ ...
Page 132
... MPU access over the address/data bus. 0x3C—Error Status (ERR_STATUS) ERR_STATUS is a read-clear register in RS8953B. Reading ERR_STATUS forces its contents to 0. Transmit and receive HDSL channel errors and DPLL errors are reported individually in ERR_STATUS, where they are indefinitely latched until cleared. The MPU reads ERR_STATUS to determine the cause of a TX_ERR or RX_ERR interrupt ...
Page 133
... RS8953B/8953SPB HDSL Channel Unit 4.15 PRA Transmit Read Table 4-12. PRA Transmit Read Registers Address Register Label 0x40 TX_PRA_CTRL0 0x41 TX_PRA_CTRL1 0x42 TX_PRA_MON1 0x43 TX_PRA_E_CNT 0x45 TX_PRA_CODE 0x46 TX_PRA_MON0 0x47 TX_PRA_MON2 0x40—PRA Transmit Control Register 0 (TX_PRA_CTRL0 E_MODE[1:0] SA8_MODE Controls the behavior of Sa4 bits transmitted towards the HDSL link, as follows: ...
Page 134
... Enable—Use TMSYNC input pin as a qualifier of the frame, and force the synchronization state machine to HUNT mode 1 = Disable—Use TMSYNC input as a qualifier of multiframe Code CRC4 Bits 00 Transparent 01 All 1 10 Re-calculated 11 Illegal 0 = Transparent 1 = From bits buffer 0 Conexant RS8953B/8953SPB HDSL Channel Unit SYNCHR_EN PRA_EN N8953BDSB ...
Page 135
... RS8953B/8953SPB HDSL Channel Unit Enables to override all 32 slots of an PCM frame except Slot 0, transmitted towards the HDSL AIS link, with a constant pattern: AIS enables to achieve framed AIS. To achieve unframed arbitrary AUX pattern NOTE: generation, use the existing feature of the channel unit. ...
Page 136
... The 4 bits of this register represent the original number of the relative frame with which synchronization was achieved. This is relevant only if bit SYNCH_STATE of TX_PRA_MON0 reads 1. 4- — Not synchronized 1 = Synchronized 4 3 — Conexant RS8953B/8953SPB HDSL Channel Unit — CRC error2 CRC error1 TX_PRA_MON2[3:0] N8953BDSB ...
Page 137
... RS8953B/8953SPB HDSL Channel Unit 4.16 PRA Transmit Write Table 4-13. PRA Transmit Write Registers Address Register Label 0x70 TX_PRA_CTRL0 0x71 TX_PRA_CTRL1 0x72 TX_BITS_BUFF1 0x73 TX_PRA_TMSYNC_OFFSET 0x74 TX_BITS_BUFFO 0x70—PRA Transmit Control Register 0 (TX_PRA_CTRL0 E_MODE[1:0] SA8_MODE Controls the behavior of Sa4 bits transmitted towards the HDSL link, as follows: ...
Page 138
... Enable. Use TMSYNC input pin as a qualifier of the frame and force synchronization state machine to HUNT mode Disable. Use TMSYNC input as a qualifier of multiframe. Code CRC4 Bits 00 Transparent 01 All ‘1’s 10 Re-calculated 11 Illegal 0 = Transparent 1 = From bits buffer 0 Conexant RS8953B/8953SPB HDSL Channel Unit SYNCHR_EN PRA_EN N8953BDSB ...
Page 139
... Transmit TMSYNC offset Register (TX_PRA_TMSYNC_OFFSET The value of this register is used to enable the accommodation of the RS8953B to any TMSYNC signal shape. When programmed to 0x00, the PRA circuitry assumes that the positive edge of the TMSYNC input signal coincides with the first bit of an PCM framer. N8953BDSB ...
Page 140
... PCM to HDSL 5 _1, _2, _3, _4 location of the data stream, in the PCM used in Frames 1 and used in Frames 3 and 11 used in Frames 7 and 15. 6 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
Page 141
... RS8953B/8953SPB HDSL Channel Unit 4.17 PRA Receive Read Table 4-14. PRA Receive Read Registers Address Register Label 0x80 RX_PRA_CTRL0 0x81 RX_PRA_CTRL1 0x82 RX_BITS_BUFF1 0x83 RX_PRA_E_CNT 0x84 RX_PRA_CRC_CNT 0x85 RX_PRA_CODE 0x86 RX_PRA_MON0 0x87 RX_PRA_MON2 0x80—PRA Receive Control Register 0 (RX_PRA_CTRL0 E_MODE[1:0] SA8_MODE Controls the behavior of Sa4 bits transmitted towards PCM, as follows: ...
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... Enable synchronization and force HUNT mode. Take RMSYNC as indicator of frame Disable synchronization. Take RMSYNC as multiframe indicator. Code E-bits 00 Transparent 01 All 1 10 Re-calculated 11 Illegal 0 = Transparent 1 = From bits buffer Disable (Normal 0xFF Conexant RS8953B/8953SPB HDSL Channel Unit E-bits Forced to SYNCHR_EN PRA_EN N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Clears the RX_E counter, as follows: RST_E_CNT Clears the RX_CRC counter, as follows: RST_CRC_CNT The value of this register takes effect starting with the next PCM multiframe NOTE: following the write access cycle completion. 0x82—PRA Receive Monitor Register 1 (RX _PRA_MON1) ...
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... HDSL to PCM direction. 5 _1, _2, _3, _4 location of the data stream, in the HDSL to PCM — Not synchronized 1 = Synchronized 4 3 — Conexant RS8953B/8953SPB HDSL Channel Unit — — CRC error2 CRC error1 2 ...
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... RS8953B/8953SPB HDSL Channel Unit 4.18 PRA Receive Write Table 4-15. PRA Receive Write Registers Address Register Label 0xB0 RX_PRA_CTRL0 0xB1 RX_PRA_CTRL1 0xB2 RX_BITS_BUFF1 0xB4 RX_PRA_BUFF0 0xB0—PRA Receive Control Register 0 (RX_PRA_CTRL0 E_MODE[1:0] SA8_MODE Controls the behavior of Sa4 bits transmitted towards PCM, as follows: ...
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... Disable synchronization. Take RMSYNC as multiframe indicator. Code CRC4 Bits 00 Transparent 01 All 1 10 Re-calculated 11 Illegal 0 = Transparent 1 = From bits buffer Disable (Normal 0xFF AIS must be activated with reset_e_cnt = Counter enabled 1 = Clear the E-receive counter Conexant RS8953B/8953SPB HDSL Channel Unit SYNCHR_EN PRA_EN N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Clears the RX_CRC counter, as follows: RST_CRC_CNT The value of this register takes effect starting with the next PCM multiframe, NOTE: following the write access cycle completion. 0xB2—PRA Receive Bits Buffer 1 (RX_BITS_BUFF1 _MASK Sa _MASK — The value of this register is only relevant if its corresponding MODE bit of RX_PRA_CTRL0 is set. A new written value takes effect starting with the next PCM multiframe following the register write access cycle completion ...
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... HDSL to PCM direction used in Frames 5 and 13 4-80 location of the data stream, in the HDSL to PCM 5 _1, _2, _3, _4 location of the data stream, in the used in Frames 1 and used in Frames 7 and 15. 6 Conexant RS8953B/8953SPB HDSL Channel Unit _2 is used in Frames 3 and 11. N8953BDSB ...
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... Applications The following chapter shows typical interconnections of the RS8953B HDSL channel unit: • Conexant HDSL Transceiver • Bt8370 E1/T1 Primary Rate Framer • Motorola 68302 16-bit Processor • Intel 8051 8-bit Processor N8953BDSB 5 Conexant 5-1 ...
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... Applications 5.1 Interfacing to a Conexant HDSL Transceiver 5.1 Interfacing to a Conexant HDSL Transceiver Figure 5-1 channel unit and a Conexant HDSL transceiver. Figure 5-1. RS8953B HDSL Channel Unit to Conexant HDSL Transceiver Interconnection TDAT1 QCLK1 RDAT1 BCLK1 RS8953B TDAT2 QCLK2 RDAT2 BCLK2 TDAT3 QCLK3 RDAT3 BCLK3 Loop Quat Clock (QCLKn) when low, qualifies the sign bit on the Loop Receive Data (RDATn). ...
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... RS8953B/8953SPB HDSL Channel Unit 5.2 Interfacing to the Bt8370 E1/T1 Framer Figure 5-2 channel unit and the Bt8370 E1/T1 framer. Figure 5-2. RS8953B HDSL Channel Unit to Bt8360 DS1 Framer Interconnection RSBCKI/RCKO Bt8370 TSBCKI/TCKI N8953BDSB illustrates a typical interconnection between the RS8953B HDSL TCLK TSER RPCMO TMSYNC RMSYNC TPCMI ...
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... Interfacing to the 68302 Processor 5.3 Interfacing to the 68302 Processor Figure 5-3 channel unit and the 68302 processor. Figure 5-3. RS8953B to 68302 Processor Interconnection A[15] AS MC68302 DS R/W A[7:0] D[7:0] IRQ6 5-4 illustrates a typical interconnection between the RS8953B HDSL VCC MPUSEL CS* ALE RD* WR* Mux AD[7:0] Logic INTR* Conexant RS8953B/8953SPB HDSL Channel Unit ...
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... RS8953B/8953SPB HDSL Channel Unit 5.4 Interfacing to the 8051 Controller Figure 5-4 channel unit and the 8051 controller. Figure 5-4. RS8953B HDSL Channel Unit to 8051 Controller Interconnection 8051 AD[15] AD[7:0] INT0 N8953BDSB illustrates a typical interconnection between the RS8953B HDSL ALE WR RD Conexant 5.0 Applications 5.4 Interfacing to the 8051 Controller ...
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... Applications 5.5 References 5.5 References Applicable specifications: • Bellcore TA-NWT-001210 • Bellcore FA-NWT-001211 • ETSI RTR/TM–03036 • CCITT Recommendation G.704 • Bellcore TR-NWT-000499 5-6 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Table 6-1. Absolute Maximum Ratings Symbol Parameter VCC Supply Voltage V Voltage on Any Signal Pin I T Storage Temperature ST T Vapor Phase Soldering VSOL Temperature (1 minute) Thermal Resistance ...
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... I I Three-State Leakage Current OZ C Input Capacitance IN C Output Capacitive Loading LD C High-Impedance Output Capacitance Z I Short Circuit Output Current OSC 6-2 Minimum 2.4 200 2 40 –10 –10 37 Conexant RS8953B/8953SPB HDSL Channel Unit Maximum Units 21.1 mA 11.6 mA 9.8 mA 13.8 mA 10 500 A 10 ...
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... RS8953B/8953SPB HDSL Channel Unit 6.1.3 Timing Requirements Figure 6-1. Input Clock Timing Input Clock Table 6-4. Clock Timing Requirements Symbol Parameter 1/ Tp Mclk Frequency (Pll_dis = 0; Pll_mul = 16) Mclk Frequency (Pll_dis = 0; Pll_mul = 8) Mclk Frequency (Pll_dis = 1) Tclk, Exclk Frequency Bclkn Frequency Tck Frequency Th Clock Width High Tl Clock Width Low ...
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... TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC TSER, INSDAT, TMSYNC Test Access Inputs TMS, TDI Conexant RS8953B/8953SPB HDSL Channel Unit Maximum Units ns ns RCLK_SEL RCLK_INV (CMD_2) (CMD_7) — ...
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... RS8953B/8953SPB HDSL Channel Unit 6.1.4 Switching Characteristics Figure 6-3. Output Clock and Data Timing Output Clock Falling Edge Outputs Thld Rising Edge Outputs Table 6-7. Clock and Data Switching Characteristics Symbol Parameter 1/Tp SCLK Frequency RCLK Frequency Th Clock Width High Tl Clock Width Low Tr Clock Rise Time ...
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... MSYNC, INSERT PCM Receive Channel Outputs RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP RSER, RMSYNC, DROP Test Access Outputs TDO Conexant RS8953B/8953SPB HDSL Channel Unit RCLK_SEL RCLK_INV (CMD_2) (CMD_7) — 00 — — 01 — ...
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... RS8953B/8953SPB HDSL Channel Unit 6.1.5 MPU Interface Timing Motorola- (MPUSEL = 1) and Intel- (MPUSEL = 0) style microprocessor bus timing, as follows: Table 6-9. MPU Interface Timing Requirements Symbol Parameter 1 ALE Pulse-Width High 2 Address Input Setup to ALE Falling 3 Address Input Hold after ALE Low 5 Data Input Setup to End of Write Pulse ...
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... Figure 6-4. MPU Write Timing, MPUSEL = 1 ALE AD[7:0] CS* RD* (Data Strobe) WR* (Write Enable) INTR* Figure 6-5. MPU Read Timing, MPUSEL = 1 ALE AD[7:0] RD* CS* WR* (Read Enable) 6 ADDRESS DATA INPUT ADDRESS DATA OUTPUT Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Figure 6-6. MPU Write Timing, MPUSEL = 0 ALE 1 2 AD[7:0] WR* CS* INTR* Figure 6-7. MPU Read Timing, MPUSEL = 0 ALE 1 2 AD[7:0] RD* CS* N8953BDSB 3 ADDRESS DATA INPUT ADDRESS DATA OUTPUT Conexant 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings 9 14 ...
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... Electrical and Timing Specifications 6.2 Mechanical Specifications 6.2 Mechanical Specifications Figure 6-8. 68-Pin PLCC Package Drawing 6-10 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... RS8953B/8953SPB HDSL Channel Unit Figure 6-9. 80–Pin PQFP Mechanical Specification N8953BDSB 6.0 Electrical and Timing Specifications 6.2 Mechanical Specifications Conexant 6-11 ...
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... Electrical and Timing Specifications 6.2 Mechanical Specifications 6-12 Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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Acronyms, Abbreviations and Notation 7.1 Arithmetic Notation 7.1.1 Bit Numbering The Least Significant Bit (LSB) having the lowest number represents the lowest number within a bit. 7.1.2 Acronyms and Abbreviations N8953BDSB 7 AIS Alarm Indication Signal 2B1Q 2 Binary, ...
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... Acronyms, Abbreviations and Notation 7.1 Arithmetic Notation 7-2 VCXO Voltage-Controlled Crystal Oscillator Conexant RS8953B/8953SPB HDSL Channel Unit N8953BDSB ...
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... Appendix A A.1 Differences Between Bt8953A and RS8953B Table A-1. Pin Definitions Pin Number 68 Pin 80 Pin Signal PLCC PQFP 19 13 VCC 27 23 VCC 48 48 PLLVCC 49 49 VCC (SCAN_MD VCC 44 43 LP1 45 45 LP2 N8953BDSB A Bt8953A (5.0 V) Description Signal 5.0 V VCC 5.0 V VCC 5.0 V PLLVCC 5.0 V VCC (SCAN_MD) 5.0 V VCC ...
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... Appendix A A.1 Differences Between Bt8953A and RS8953B Table A-2. Power Consumption Configuration Maximum 528 Kbps on single DSL / 2.048 Mbps on PCM 1040 Kbps on single DSL / 2.048 Mbps on PCM 1168 Kbps on single DSL / 2.048 Mbps on PCM 1T1 (1.552 Mbps on single DSL / 1.544 Mbps on PCM) 2T1 (784 Kbps on 2 DSL / 1.544 Mbps on PCM) 1E1 (2 ...
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... Appendix B: Bt8953A/RS8953B Product Bulletin B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B While in repeater mode (REPEAT_EN = 1 for CH1 and CH2), a BCLK1 to BCLK2 phase difference of 180 degrees, +/- 5 nSec, will result in corrupted data transfer. All other phase relationships are acceptable. ...
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... Appendix B : Bt8953A/RS8953B Product Bulletin B.1 BCLK Phase Constraints In Repeater Mode; Non-Conformance Product Affected: Bt8953A and RS8953B HCLK BCLK BCLK1 QCLK QCLK1 TDAT TDAT1 RDAT RDAT1 HTU-R Bt8953A/RS8953B Zipwire Transceiver B-2 1 CLK D 0 MCLK BCLK2 0 CLK D QCLK2 1 TDAT2 1 RDAT2 0 Conexant RS8953B/8953SPB HDSL Channel Q MCLK ...
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... Phone: (852) 2827 0181 Fax: (852) 2827 6488 Web Site www.conexant.com India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 World Headquarters Conexant Systems, Inc. 4311 Jamboree Road Korea P. O. Box C Phone: (82 2) 565 2880 Newport Beach, CA Fax: (82 2) 565 1440 92658-8902 ...