TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 92

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
INTCLR
Interrupt
clear control
Name
(4) Interrupt request flag clear register
(5) Micro DMA start vector registers
start vector, as given in Table 3.6.1 to the register INTCLR.
operation after execution of the DI instruction.
corresponds to DMA. The interrupt source whose micro DMA /HDMA start vector
value matches the vector set in one of these registers is designated as the micro DMA
/HDMA start source.
(HDMACBn) value reaches “0”, the micro DMA /HDMA transfer end interrupt
corresponding to the channel is sent to the interrupt controller, the micro DMA /HDMA
start vector register is cleared, and the micro DMA /HDMA start source for the channel
is cleared. Therefore, in order for micro DMA /HDMA processing to continue, the micro
DMA /HDMA start vector register must be set again during processing of the micro
DMA /HDMA transfer end interrupt.
one channel, the lowest numbered channel takes priority.
for two different channels, the interrupt generated on the lower-numbered channel is
executed until micro DMA /HDMA transfer is complete. If the micro DMA /HDMA start
vector for this channel has not been set in the channel’s micro DMA /HDMA start
vector register again, micro DMA /HDMA transfer for the higher-numbered channel
will be commenced. (This process is known as micro DMA /HDMA chaining.)
The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA
For example, to clear the interrupt flag INT0, perform the following register
These registers assign micro DMA/HDMA processing to sets which source
When the micro DMA transfer counter (DMACn) or HDMA transfer counter B
If the same vector is set in the micro DMA /HDMA start vector registers of more than
Accordingly, if the same vector is set in the micro DMA /HDMA start vector registers
Address
(Prohibit
RMW)
F8H
INTCLR
CLRV7
7
0
←
0AH
CLRV6
92CF29A-90
6
0
CLRV5
5
0
; Clears interrupt request flag INT0.
CLRV4
Interrupt vector
4
0
W
CLRV3
3
0
CLRV2
2
0
TMP92CF29A
CLRV1
2009-06-11
1
0
CLRV0
0
0