TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 253

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

(g) <RSESTA>
(h) <RSEDN>
(i)
generated from the ECC for written data and the ECC for read data. Setting <RSESTA> to
“1” starts this calculation.
bit should be set to “0”.
read from the NDECCRDn register is written to the redundant area in the NAND Flash.
For a read operation, this bit should be set to “1” (decode). In this case, valid data is read
from the NAND Flash and the ECC written in the redundant area is also read to generate
an intermediate code for calculating the error address and error bit position.
this bit should be set to “0”.
an ECC calculator. The latter is used to calculate the error address and error bit position.
generated from the ECC for written data and the ECC for read data. At this time, no special
care is needed if ECC generation and error calculation are performed serially. If these
operations need to be performed parallely, the intermediate code used for error calculation
must be latched while the calculation is being performed. The <RSECCL> bit is provided to
enable this latch operation.
generator can generate the ECC for another page without problem while the ECC
calculator is calculating the error address and error bit position. At this time, the ECC
generator can perform both encode (write) and decode (read) operations.
calculator are updated as the data in the ECC generator is updated.
Flow of data
The <RSEDN> bit is used only for Reed-Solomon codes. When using Hamming codes, this
For a write operation, this bit should be set to “0” (encode) to generate ECC. The ECC
When <RSECCL> is set to “0”, the latch is released and the contents of the ECC
The <RSESTA> bit is used only for Reed-Solomon codes.
The error address and error bit position are calculated using an intermediate code
The <RSECCL> bit is used only for Reed-Solomon codes. When using Hamming codes,
The Reed-Solomon processing unit is comprised of two elements: an ECC generator and
The error address and error bit position are calculated using an intermediate code
When <RSECCL> is set to “1”, the intermediate code is latched so that the ECC
<RSECCL>
Reed-Solomon
Reed-Solomon
Generator
Calculator
F/F 80bit
ECC
ECC
92CF29A-251
<RSECCL>= “0” Latch_OFF
<RSECCL>= “1” Latch_ON
NDECCRDn
Register
TMP92CF29A
2009-06-11