TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 513

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

(h) <EDGE0>
(m) <CK07:00>
(n) <WS05:00>
(i) <WLVL0>
(j) <TEMP0>
(k) <FSEL0>
(l) <CLKS0>
the rising edge of clock.
falling edge of clock.
data format, set <SYSCKE0>=“1”, <CNTE0>=“0” and <TXE0>=“0”.
<WLVL0>. Refer the “FIFO buffer and data format” in details.
Before changing the data format, set <SYSCKE0>= “1”, <CNTE0>= “0” and
<TXE0>=“0”.
in details.
the data format, set <SYSCKE0>=“1”, <CNTE0>=“0” and <TXE0>=“0”.
time. In details, refer the chapter of PLL, please.
changing the counter value, set <SYSCKE0>=“1”, <CNTE0>=“0” and <TXE0>=“0”.
changing the counter value, set <SYSCKE0>=“1”, <CNTE0>=“0” and <TXE0>=“0”.
This bit controls relation of phase between I2S0CKO and data.
<EDGE0>=“0”: the data is changed in the falling of clock, and the data is latched in
<EDGE0>=“1”: the data is changed in the rising of clock, and the data is latched the
It is not possible to change phase during data transmission. Before changing the
This bit controls phase of Word Select signal: I2S0WS
I2S0WS signal always out “1” level first. The order of data output changes by
It is not possible to change phase of Word Select signal during data transmission.
This bit is empty flag of output FIFO buffer.
<TEMP0>=“1”: FIFO buffer is empty, <TEMP0>=“0”: remain data in FIFO buffer.
This bit is read only. FIFO buffer is cleared by <TXE0>=“0”
This bit controls sound mode: Stereo / Monaural
<FSEL0>=“0”: Stereo, <FSEL0>=“1”: Monaural. Refer the chapter of “Data format”
It is not possible to change sound mode during data transmission. Before changing
This bit controls source clock to I
<CLKS0>=“0”: f
In case of using f
These bits are set counter value of clock generator. [I2S0CK]
It is not possible to change these counter value during data transmission. Before
These bits are set counter value of clock generator. [I2S0WS]
It is not possible to change these counter value during data transmission. Before
SYS
PLL
is supplied, <CLKS0>=“1”: f
, before set f
92CF29A-511
2
S circuit: f
PLL
clock, please take care set-up time: Lock-Up
SYS
/ f
PLL
PLL
is supplied.
.
TMP92CF29A
2009-06-11