TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 218

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

3.10.2.5 DMA-Function Bank Registers
the high-speed data transfer by enabling the internal DMAC to become the bus master.
(Please refer to Section 3.7, “DMA Controller”.)
registers for the CPU and LCDC. Regardless of the settings of the bank registers for
program, read and write data of the CPU, the banks to be used as source address memory
and destination address memory are specified individually during DMA operations.
performed by dividing those channels into 2 groups. The DMA channels with the
even-channel number, 0, 2 and 4, are classified into the E-group (ES and ED groups); while
the channels with the odd-channel number, 1 and 3, are classified into the O-group (OS and
OD groups). These registers cannot specify bank numbers for each channel, but specifies
one bank number for all the channels in the same group.
the LOCAL-X area, and also specify bank 2 for storing DMA-destination addresses in the
LOCAL-Y area. If the DMA operation for channel 0 is initiated Assume that the source and
destination addresses specified by the DMA operation, which is described in Section 3.7,
are set into the LOCAL-X and LOCAL-Y areas, respectively. Then, if the DMA operation
for channel 0 is initiated, bank 1 in the LOCAL-X area is configured as the source address
memory, and bank 2 in the LOCAL-Y area is configured as the destination address memory.
(Example)
The TMP92CF29A supports not only the read and write operations of the CPU, but also
These registers are provided specially for the DMA operation, separately from the bank
The DMAC of the TMP92CF29A supports six channels, and the bank control is
The following example shows how to specify bank 1 for storing DMA-source addresses in
DMA operation for channel 0 is started
ldw
ldw
(localesx), 8001h
(localedy), 8002h
92CF29A-216
;
;
Specify DMA-source bank number for channel 0
Specify DMA-destination bank number for channel 0
TMP92CF29A
2009-06-11