TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 166

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TMP92xy29FG

Manufacturer Part Number
TMP92xy29FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy29FG

Package
QFP176
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
98
Power Supply Voltage(v)
3.0 to 3.6
3.8.17
input or output. Resetting sets port P3 to P5 to input port and output latch to “0”.
output pin for timer (TA7OUT), as an input pin for timers (TB0IN0, TB1IN0), and as an
input pin for external interruption (INT5 to INT7), serial transfer SIO0 (TXD0, RXD0,
SCLK0,
pin for timer (TB0OUT0).
interruption controller.
INT7 don’t depend on IIMC1 register setting.
TBnMOD<TBnCPM1:0>.
Port P (PP3 to PP7)
Ports P3 to P5 are 3-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port, P3 to P5 can also function as an
Port P6 is 1-bit output port. Resetting sets output latch to “0”.
In addition to functioning as an output port, PP6 and PP7 can also function as an output
Setting in the corresponding bits of PPCR and PPFC enables the respective functions.
The edge select for external interruption is determined by the IIMC register in the
In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and
CTS ), SIO1 (TXD1, RXD1, SCLK1,
TA7OUT
INT5
0
Direction control
(on bit basis)
Output latch
(on bit basis)
PPFC write
PP write
Function
Reset
PPCR write
control
PP read
R
<PP1F2>
Figure 3.8.44 Port P3
92CF29A-164
A
B
Selector
Rising/Falling selection
S
IIMC<I5LE, I5EDGE>
Level/edge selection
Selector
S
and
CTS ).
B
TXD0
TXD1
A
1
<PP4F2>
A
B
<PP1F2>
Selector
INT6 and INT7 operate by setting
S
<PP1F2>
Selector
B
A S
Open-drain possible
PPFC2<PP0F2>
TMP92CF29A
2009-06-11
PP3 (INT5,TA7OUT,
TXD0, TXD1)

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