TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 178

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

PVFC
(00ABH)
PVFC2
(00A9H)
PV
(00A8H)
PVCR
(00AAH)
PVDR
(009DH)
<PV7F>
PV7 setting
<PV7C>
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: A read-modify-write operation cannot be performed for the registers PVCR, PVFC and PVFC2.
Input port
Reserved
0
0: CMOS
1: Open
(Output latch register is
Refer to following table
Data from external port
PV7F2
-drain
Input/Output buffer
PV7C
PV7D
PV7F
0: Input 1: Output
PV7
drive register for
7
7
7
7
7
standby mode
0
−
0
−
0
−
1
−
cleared to “0”)
Output port
SCL I/O
R/W
R/W
W
W
1
−
0: CMOS
1: Open
PV6F2
-drain
PV6C
PV6D
PV6F
PV6
6
6
6
0
−
6
−
6
0
−
0
−
1
Figure 3.8.55 Register for Port V
PV6 setting
<PV6F>
<PV6C>
Port V function register 2
0
1
Port V function register
Port V control register
Port V drive register
5
5
5
5
5
92CF29A-176
Port V register
Input port
Reserved
0
4
4
4
4
4
Output port
SDA I/O
3
3
3
3
3
1
2
2
2
2
2
1
1
1
1
1
TMP92CF29A
0
0
0
0
0
2009-06-11