TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 758

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

I2S0CTL
Symbol
I2S0BUF
I2S0C
(22) I
I
Transmis-
sion
Buffer
Register0
I
Control
Register0
I
Divider
Value
Setting
Register
2
2
2
S
Name
S
S0
2
S
Address
(Prohibit
180AH
180BH
RMW)
1808H
1809H
1800H
Transmit
0: Stop
1: Start
Source
clock
0: f
1: f
B015
B031
15 14
31 30
CLKS0
TXE0
CK07
SYS
PLL
R/W
R/W
0
0
0
B014
B030
Counter
control
0: Clear
1: Start
B013
13
29
B09
*CNTE0
CK06
R/W
0
0
B012
B028
12
28 27 26
92CF29A-756
B011
B027
11 10
WS05
CK05
Divider value for CK signal (8-bit counter)
0
0
B010
B026
Transmission buffer register (FIFO)
Transmission buffer register (FIFO)
Transmis
-sion start
BIT
0:MSB
1:LSB
Stereo
/monaural
0: Stereo
1:Monaural
B009
B025
25
9
FSEL0
WS04
CK04
DIR0
R/W
R/W
Divider value for WS signal (6-bit counter)
0
0
0
0
B008
B024
24
Undefined
Undefined
8
R/W
W
W
Bit length
0: 8 bits
1:16 bits
Condition of
transmission
FIFO
0: data
1: None
data
B007
B023
23
7
TEMP0
WS03
CK03
BIT0
R/W
R
0
1
0
0
B006
B022
22
6
R/W
Output format
00: I
10: Right
01: Left
11:Reserved
WS level
0:low left
1:high left
B005
B021
DTFMT01
21
5
WLVL0
WS02
CK02
R/W
R/W
2
0
S
0
0
0
B004
B020
20
4
Clock edge
for data
output
0:Falling
1:Rising
B003
B019
DTFMT00 SYSCKE0
19
3
EDGE0
WS01
CK01
R/W
R/W
0
0
0
0
B002
B018
TMP92CF29A
18 17
2
2009-06-11
System
clock
0:Disable
1:Enable
Clock enable
(After trans-
mission)
0:Operate
1:Stop
B001
B017
1
CLKE0
WS00
CK00
R/W
R/W
0
0
0
0
B000
B016
16
0