TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 278

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

3.13.2
fc
Note: TMR45 and TMR67 can be selected low-frequency clock(fs) instead of external clock input.
Operation of Each Circuit
<GEAR2:0>
Clock gear
100(1/16)
100(1/16)
(1)
SYSCR1
(2)
selection
000(1/1)
001(1/2)
010(1/4)
011(1/8)
000(1/1)
001(1/2)
010(1/4)
011(1/8)
selected using the prescaler clock selection register SYSCR0<PRCK>.
timer control register. Setting <TA01PRUN> to “1” starts the count; setting
<TA01PRUN> to “0” clears the prescaler to “0” and stops operation. Table 3.13.2
shows the various prescaler output clock resolutions.
timer counter’s operation depends on the prescaler’s input timing.)
clock specified by TA01MOD.
via the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock
setting is specified by the value set in TA01MOD<TA01CLK1:0>.
the overflow output from UC0 is used as the input clock. In any mode other than
16-bit timer mode, the input clock is selectable and can either be one of the internal
clocks φT1, φT16 or φT256, or the comparator output (The match detection signal)
from TMRA0.
<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up
counters and to control their count. A reset clears both up counters, stopping the
timers.
Prescaler
A 9-bit prescaler generates the input clock to TMRA01.The clock φT0TMR is
The prescaler operation can be controlled using TA01RUN<TA0PRUN> in the
(Although the prescaler and the timer counter can be started separately, the
Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the
The input clock for UC0 is selectable and can be either the external clock input
The input clock for UC1 depends on the operation mode. In 16-bit timer mode,
For each interval timer the timer operation control register bits TA01RUN
Table 3.13.2 Prescaler Output Clock Resolution
Prescaler of
clock gear
SYSCR0
<PRCK>
0(1/2)
1(1/8)
92CF29A-276
1/2
−
φT1(1/2)
fc/128
fc/128
fc/256
fc/512
fc/16
fc/32
fc/64
fc/32
fc/64
fc/8
φT4(1/8)
fc/1024
fc/2048
fc/128
fc/256
fc/512
fc/128
fc/256
fc/512
fc/32
fc/64
Timer counter input clock
TAxxMOD<TAxCLK1:0>
Prescaler of TMRA
φT16(1/32)
fc/1024
fc/2048
fc/1024
fc/2048
fc/4096
fc/8192
fc/128
fc/256
fc/512
fc/512
φT256(1/512)
fc/131072
fc/16384
fc/32768
fc/16384
fc/32768
fc/65536
fc/2048
fc/4096
fc/8192
fc/8192
TMP92CF29A
2009-06-11