SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 814

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

43.12 SMC Timings
43.12.1
43.12.2
Table 43-28. SMC Read Signals - NRD Controlled (READ_MODE = 1)
Table 43-29. SMC Read Signals - NCS Controlled (READ_MODE= 0)
814
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
Symbol
1
2
3
4
5
6
7
AT91SAM9XE128/256/512 Preliminary
Timing Conditions
Read Timings
Parameter
Data Setup before NRD High
Data Hold after NRD High
Data Setup before NRD High
Data Hold after NRD High
A2 - A25 Valid before NRD High
NCS low before NRD High
NRD Pulse Width
Parameter
NBS0/A0, NBS1, NBS2/A1, NBS3,
SMC timings are given in worst case conditions (1.65V/3.0V, 85°C).
Timings are given assuming a capacitance load on data, control and address pads:
Table 43-27. Capacitance Load
In the following tables t
Supply
3.3V
1.8V
VDDIOM supply
VDDIOM supply
HOLD or NO HOLD SETTINGS (nrd hold … 0, nrd hold =0)
NO HOLD SETTINGS (ncs rd hold = 0)
NO HOLD SETTINGS (nrd hold = 0)
C
50pF
30 pF
LOAD
HOLD SETTINGS (nrd hold … 0)
nrd pulse - ncs
(nrd setup +
(nrd setup +
CPMCK
nrd pulse)*
t
t
nrd pulse *
t
rd setup) *
CPMCK
CPMCK
CPMCK
Max
1.8V
12.6
-7.2
1.8V
9
0
represents the MCK period.
-3.0
-7.1
-0.3
Min
Min
nrd pulse - ncs
(nrd setup +
(nrd setup +
nrd pulse)*
t
t
nrd pulse *
t
rd setup) *
CPMCK
CPMCK
CPMCK
12.61
3.3V
3.3V
-7.2
9
0
-0.3
-3.1
-7.2
1.8V
1.8V
Max
Max
3.3V
3.3V
6254C–ATARM–22-Jan-10
Units
Units
ns
ns
ns
ns
ns
ns
ns