SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 17

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

7.2
7.2.1
7.2.2
6254C–ATARM–22-Jan-10
Bus Matrix
Matrix Masters
Matrix Slaves
The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can
perform an access concurrently with others, depending on whether the slave it accesses is
available.
Each Master has its own decoder, which can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Master 4
Master 5
Slave 0
Slave 1
Slave 2
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
• Remap Command
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal ROM or internal Flash
– Selection is made by General purpose NVM bit sampled at reset
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
or fixed default master
internal ROM boot, one for internal flash boot, one after remap
(ROM or Flash)
List of Bus Matrix Masters
List of Bus Matrix Slaves
AT91SAM9XE128/256/512 Preliminary
Internal SRAM
Internal ROM
USB Host User Interface
External Bus Interface
ARM926
ARM926 Data
Peripheral DMA Controller
USB Host Controller
Image Sensor Controller
Ethernet MAC
™
Instruction
17