SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 48

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.3.7.1
48
AT91SAM9XE128/256/512 Preliminary
Status Registers
ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when
BL or BLX instructions are executed within interrupt or exception routines. There is another reg-
ister called Saved Program Status Register (SPSR) that becomes available in privileged modes
instead of CPSR. This register contains condition code flags and the current mode bits saved as
a result of the exception that caused entry to the current (privileged) mode.
In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call
Standard (APCS) which defines:
For more details, refer to ARM Software Development Kit.
The Thumb state register set is a subset of the ARM state set. The programmer has direct
access to:
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see
the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12).
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The
program status registers:
Figure 11-2. Status Register Format
Figure 11-2
• constraints on the use of registers
• stack conventions
• argument passing and result return
• Eight general-purpose registers r0-r7
• Stack pointer, SP
• Link register, LR (ARM r14)
• PC
• CPSR
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operation mode
• N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
shows the status register format, where:
N Z C V Q
31 30 29 28 27
24
J
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Reserved
I F T
7 6 5
Mode
0
Mode bits
Thumb state bit
FIQ disable
IRQ disable
6254C–ATARM–22-Jan-10