SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 27
SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 27 of 860
- Download datasheet (13Mb)
8.2.3
8.2.4
8.2.5
6254C–ATARM–22-Jan-10
SDRAM Controller
Error Corrected Code Controller
I/O Drive Selection
The purpose of this control is to adapt the signal to the frequency. Two bits enable the user to
select High or Low Drive for memory data/addresses/control signals.
Setting the EBI_DRIVE field [17:16] in the EBI Chip Select Assignement Register (EBI_CSA)
located in the Chip Select Interface of the Bus Matrix, enables control of the EBI.
• Supported devices:
• Numerous configurations supported
• Programming facilities
• Energy-saving capabilities
• Error detection
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
• Hardware error corrected code generation
• Supports NAND Flash and SmartMedia devices with 8- or 16-bit data path
• Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes
• Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit data
• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes
• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes
specified by software
path
with 8-bit data path
with 8-bit data path
– Standard and Low Power SDRAM (Mobile SDRAM)
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Self-refresh, power down and deep power down modes supported
– Refresh Error Interrupt
– Detection and correction by software
AT91SAM9XE128/256/512 Preliminary
27
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