SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 21

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1
8.1.1
8.1.2
8.1.3
8.1.4
6254C–ATARM–22-Jan-10
Embedded Memories
AT91SAM9XE128
AT91SAM9XE256
AT91SAM9XE512
ROM Topology
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals
and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap, refer to
A complete memory map is presented in
The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs.
Each of these two programs is stored on 16-Kbyte Boundary of FFPI and the program executed
• 32 Kbytes ROM
• 16 Kbytes Fast SRAM
• 128 Kbytes Embedded Flash
• 32 Kbytes ROM
• 32 Kbytes Fast SRAM
• 256 Kbytes Embedded Flash
• 32 Kbytes ROM
• 32 Kbytes Fast SRAM
• 512 Kbytes Embedded Flash
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
– Single Cycle Access at full matrix speed
AT91SAM9XE128/256/512 Preliminary
Table 8-3, “Internal Memory Mapping,” on page 25
Figure 8-1 on page
20.
for details.
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