SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 52

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.3.9
11.3.10
52
AT91SAM9XE128/256/512 Preliminary
New ARM Instruction Set
Thumb Instruction Set Overview
.
Table 11-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Table 11-3
ence Manual referenced in
Table 11-4
Table 11-4.
Mnemonic
Mnemonic
MOV
ADD
SUB
CMP
TST
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
SMLAL
BLX
QADD
QSUB
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
gives the Thumb instruction mnemonic list.
shows the Thumb instruction set, for further details, see the ARM Technical Refer-
New ARM Instruction Mnemonic List
Thumb Instruction Mnemonic List
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16 *
16 bit
Signed Multiply Accumulate Long
Signed Multiply Accumulate 32 *
16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Operation
Move
Add
Subtract
Compare
Test
Table 11-1 on page
43.
Mnemonic
MVN
ADC
SBC
CMN
NEG
Mnemonic
MRRC
MCRR
MCR2
CDP2
STRD
LDRD
BKPT
STC2
LDC2
PLD
CLZ
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare to
load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Count Leading Zeroes
Alternative Load to Coprocessor
6254C–ATARM–22-Jan-10