SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 105
SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 105 of 860
- Download datasheet (13Mb)
15.3.4.2
Figure 15-5. Wake-up State
15.3.4.3
6254C–ATARM–22-Jan-10
backup_nreset
periph_nreset
Wake-up Reset
Main Supply
User Reset
POR output
proc_nreset
(nrst_out)
RSTTYP
SLCK
NRST
MCK
The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output
is active, all the reset signals are asserted except backup_nreset. When the Main Supply pow-
ers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled
during 3 Slow Clock cycles, depending on the requirements of the ARM processor.
At the end of this delay, the processor and other reset signals rise. The field RSTTYP in
RSTC_SR is updated to report a Wake-up Reset.
The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is
backed-up, the programmed number of cycles is applicable.
When the Main Supply is detected falling, the reset signals are immediately asserted. This tran-
sition is synchronous with the output of the Main Supply POR.
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in
RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behav-
ior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset
and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle
processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
Resynch.
2 cycles
XXX
Processor Startup
EXTERNAL RESET LENGTH
AT91SAM9XE128/256/512 Preliminary
= 3 cycles
= 4 cycles (ERSTL = 1)
0x1 = WakeUp Reset
Freq.
Any
XXX
105
Related parts for SAM9XE512
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
U6046BREAR WINDOW HEATING TIMER / LONG-TERM TIMER
Manufacturer:
ATMEL Corporation
Datasheet: