SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 62

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2-34
31
FCSE PID
FCSE PID Register
Addresses issued by the ARM9EJ-S core in the range 0 to 32MB are translated in
accordance with the value contained in this register. Address A becomes A + (FCSE
PID x 32MB). It is this modified address that is seen by the caches, MMU, and TCM
interface. Addresses above 32MB are not modified. The FCSE PID is a seven-bit field,
enabling 128 x 32MB processes to be mapped.
If the FCSE PID is 0, there is a flat mapping between the virtual addresses output by the
ARM9EJ-S core and the modified virtual addresses used by the caches, MMU, and
TCM interface. The FCSE PID is set to 0 at system reset.
If the MMU is disabled, then no FCSE address translation occurs.
FCSE translation is not applied for addresses used for entry based cache or TLB
maintenance operations. For these operations VA = MVA.
Table 2-26 shows the ARM instructions that can be used to access the FCSE PID
Register.
The format of the FCSE PID Register is shown in Figure 2-15.
Performing a fast context switch
You can perform a fast context switch by writing to CP15 register c13 with Opcode_2
= 0. The contents of the caches and the TLB do not have to be flushed after a fast context
switch because they still hold valid address tags. The two instructions after the FCSE
PID has been written have been fetched with the old FCSE PID, as the following code
example shows:
Copyright © 2001-2003 ARM Limited. All rights reserved.
25 24
Function
Read FCSE PID
Write FCSE PID
Table 2-26 FCSE PID Register operations
Figure 2-15 Process ID Register format
SBZ
Data
FCSE PID
FCSE PID
ARM Instruction
ARM DDI0198D
0