SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 127

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
ARM DDI0198D
TCM programmer’s model
Enabling the ITCM
Enabling the DTCM
Disabling the ITCM
Disabling the DTCM
Cachable and bufferable attributes
After reset, the behavior of the TCMs is controlled by the state of the TCM Region
Register, CP15 c9.
The ITCM can automatically be enabled at reset using the INITRAM pin. If
INITRAM is held HIGH during system reset, and the VINITHI pin is deasserted, the
ITCM is enabled with the ITCM region base set to
from the ITCM. Boot code must be pre-loaded into the TCM for this to be useful.
If INITRAM is LOW during system reset and the ITCM is disabled, the ITCM can be
enabled by writing to the ITCM Region Register. See TCM Region Register c9 on
page 2-29.
If INITRAM = 1 and VINITHI = 1, the ITCM is enabled at system reset but the
ARM926EJ-S processor boots from
Unlike the ITCM there is no way of automatically enabling the DTCM at reset. The
DTCM can only be enabled by writing to the DTCM Region Register. See TCM Region
Register c9 on page 2-29.
Disable the ITCM by clearing bit 0 of the ITCM Region Register, CP15 c9. This register
must be written using a read-modify-write operation.
Disable the DTCM by clearing bit 0 of the DTCM Region Register, CP15 c9. This
register must be written using a read-modify-write operation.
All MMU page table entries used to map TCM address space must be marked
noncachable. This is required for forward compatibility.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
.
. This allows boot code to be run
Tightly-Coupled Memory Interface
5-19