SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 150

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Bus Interface Unit
6.2.6
6.2.7
6-10
External Abort limitations
AHB clocking
from ARM926EJ-S
D/IHCLKEN
to ARM926EJ-S
AHB outputs
AHB inputs
HCLK
CLK
The ARM926EJ-S design uses a single clock, CLK. To run the ARM926EJ-S processor
at a higher frequency than the AHB system bus, a separate AHB clock enable for each
of the two bus masters is required (in a multi-AHB system each AHB system can be
running at a different frequency):
DHCLKEN
IHCLKEN
Figure 6-3 shows the relationships between CLK, HCLK, DHCLKEN, and
IHCLKEN.
For single and multi-layer AHB systems, DHCLKEN and IHCLKEN must be tied
together. If HCLK and CLK are the same frequency, the relevant HCLKEN input (or
inputs) must be tied HIGH.
CLK and HCLK must be synchronous. The skew between CLK and HCLK must be
minimized.
Only certain types of accesses cause an External Abort if an Error response is returned
for an AHB transfer. These are:
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•
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noncached read
nonbuffered write
noncached read-lock-write (SWP).
Is used to signify the rising edge of HCLK for the system data
BIU bus master.
Is used to signify the rising edge of HCLK for the system
instruction BIU bus master.
Figure 6-3 AHB clock relationships
Skew between CLK and HCLK
ARM DDI0198D