SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 60

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.3.11
2-32
TLB Lockdown Register c10
31
SBZ
29 28
The TLB Lockdown Register controls where hardware page table walks place the TLB
entry, in the set associative region or the lockdown region of the TLB, and if in the
lockdown region, which entry is written. The lockdown region of the TLB contains
eight entries. See TLB structure on page 3-31 for a description of the structure of the
TLB.
Writing the TLB Lockdown Register with the preserve bit (P bit) set to:
1
0
TLB entries in the lockdown region are preserved so that invalidate TLB operations
only invalidate the unpreserved entries in the TLB. That is, those in the set-associative
region. Invalidate TLB single entry operations invalidate any TLB entry corresponding
to the Modified Virtual Address given in Rd, regardless of their preserved state. That is,
if they are in the lockdown or set-associative regions of the TLB. See TLB Operations
Register c8 on page 2-24 for a description of the TLB invalidate operations.
The instructions you can use to program the TLB Lockdown Register are shown in
Table 2-25.
Figure 2-14 shows the TLB Lockdown Register format.
The victim automatically increments after any table walk that results in an entry being
written into the lockdown part of the TLB.
Victim
Copyright © 2001-2003 ARM Limited. All rights reserved.
26 25
Means subsequent hardware page table walks place the TLB entry in the
lockdown region at the entry specified by the victim, in the range 0 to 7.
Means subsequent hardware page table walks place the TLB entry in the
set associative region of the TLB.
Function
Read data TLB lockdown victim
Write data TLB lockdown victim
Table 2-25 Programming the TLB Lockdown Register
Figure 2-14 TLB Lockdown Register format
SBZ/UNP
Instruction
ARM DDI0198D
1 0
P