SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 149

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
If both AHB systems operate at the same frequency, DHCLKEN and IHCLKEN must
be tied together. See AHB clocking on page 6-10 for more details.
The AHB clock for each system, HCLK1 and HCLK2, must be synchronized to the
ARM926EJ-S clock signal CLK.
Memory coherency
Because of the Harvard nature of the ARM926EJ-S processor, instruction and data flow
order cannot be guaranteed, and the arbitration order of the two masters can be
considered to be arbitrary.
For single and multi-layer AHB systems:
•
•
For multi-AHB systems:
•
•
If the sequence of flow is critical, in self-modifying code for example, an Instruction
Memory Barrier (IMB) must be used to force coherency. See Chapter 9 Instruction
Memory Barrier for more details.
Copyright © 2001-2003 ARM Limited. All rights reserved.
the arbitration priority of the two masters determines which of the masters is
granted the bus, if both make a simultaneous request
if the granted master receives a Split or Retry response, the other master can be
granted the bus and complete its transaction before the split master completes.
the two systems can be operating at different frequencies
the memory slaves can insert waits and/or issue Split or Retry responses.
ARM926EJ-S
processor
DHCLKEN
IHCLKEN
D-AHB
I-AHB
Figure 6-2 Multi-AHB system example
subsystem
subsystem
D-AHB
I-AHB
D-AHB to I-AHB bridge
Bus Interface Unit
6-9