SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 35

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

2.3
2.3.1
ARM DDI0198D
Register descriptions
ID Code, Cache Type, and TCM Status Registers, c0
The following registers are described in this section:
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Register c0 accesses the ID Register, Cache Type Register, and TCM Status Registers.
Reading from this register returns the device ID, the cache type, or the TCM status
depending on the value of Opcode_2 used:
Opcode_2 = 0 ID value.
Opcode_2 = 1 instruction and data cache type.
Opcode_2 = 2 TCM status.
The CRm field Should Be Zero when reading from these registers. Table 2-4 shows the
instructions you can use to read register c0.
Writing to register c0 is Unpredictable.
Copyright © 2001-2003 ARM Limited. All rights reserved.
ID Code, Cache Type, and TCM Status Registers, c0
Control Register c1 on page 2-12
Translation Table Base Register c2 on page 2-17
Domain Access Control Register c3 on page 2-17
Register c4 on page 2-18
Fault Status Registers c5 on page 2-18
Fault Address Register c6 on page 2-20
Cache Operations Register c7 on page 2-20
TLB Operations Register c8 on page 2-24
Cache Lockdown and TCM Region Registers c9 on page 2-26
TLB Lockdown Register c10 on page 2-32
Register c11 and c12 on page 2-33
Process ID Register c13 on page 2-33
Register c14 on page 2-35
Test and Debug Register c15 on page 2-36.
Function
Read ID code
Read cache type
Read TCM status
Table 2-4 Reading from register c0
Instruction
Programmer’s Model
2-7