SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 119

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS
Internal to the ARM926EJ-S processor there are multiple sources for both the address
and chip-select outputs. The address and chip-select outputs of the TCM interface are
timing critical, however not all of the internal sources are timing critical. By combining
the DMA inputs with non-critical address and chip-select signals, DMA can be done
without impacting timing on these outputs. All other TCM interface outputs are non
timing critical, and can be multiplexed externally.
The logic used to combine the DMA chip-select with the internal chip-select signals is
designed so that if the DMA inputs are selected then the DMA chip-select is also
asserted. If this is not the case then the chip-select output value is non-deterministic
unless it is known that the TCM interface is an idle state, as indicated by the DRIDLE
or STANDBYWFI signals.
Figure 5-5 on page 5-12 shows an example of how DMA accesses interact with normal
DTCM accesses.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Early address
Late address
Early CS
Late CS
1
0
Tightly-Coupled Memory Interface
1
0
DRDMAADDR
DRADDR
DRDMAEN
DRDMACS
DRCS
5-11