SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 17

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
Chapter 6 Bus Interface Unit
Chapter 7 Noncachable Instruction Fetches
Chapter 8 Coprocessor Interface
Chapter 9 Instruction Memory Barrier
Chapter 10 Embedded Trace Macrocell Support
Chapter 11 Debug Support
Chapter 12 Power Management
Appendix A Signal Descriptions
Appendix B CP15 Test and Debug Registers
Copyright © 2001-2003 ARM Limited. All rights reserved.
Read this chapter for a description of the Bus Interface Unit (BIU)
interface to AMBA.
Read this chapter for a description of how speculative noncachable
instruction fetches are used in the ARM926EJ-S processor to improve
performance.
Read this chapter for a description of the coprocessor interface. The
chapter includes timing diagrams for coprocessor operations.
Read this chapter for the Instruction Memory Barrier (IMB) description
and how IMB operations are used to ensure consistency between data and
instruction streams processed by the ARM926EJ-S processor.
Read this chapter to understand how Embedded Trace Macrocell (ETM)
is supported in the ARM926EJ-S processor.
Read this chapter for a description of the debug interface and
EmbeddedICE-RT.
Read this chapter for a description of the power management facilities
provided by the ARM926EJ-S processor.
This appendix lists the ARM926EJ-S processor signals in functional
groups.
Read this appendix for detailed information on the registers used for test
and debug.
Preface
xvii