SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 114

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Tightly-Coupled Memory Interface
5-6
DRWD[31:0]
DRWD is the write data written into the TCM. It is valid in the same cycle as DRCS
and held stable until the penultimate cycle of the access.
DMA signals
The DMA interface allows the values of DRADDR and DRCS to be generated from a
source external to the ARM926EJ-S processor.
DRDMAEN
DRDMAEN is the DMA enable signal. When asserted it indicates that the DMA values
should be used to produce DRCS and DRADDR rather than those from the internal
ARM926EJ-S TCM controller.
DRDMACS
DRDMACS is used to generate DRCS when DRDMAEN is asserted. Because of the
way the DRDMACS signal is combined with the internal ARM926EJ-S TCM
controller, it is not valid to assert DRDMAEN without DRDMACS asserted unless the
internal TCM controller is idle (DRIDLE asserted). The relationship between these
signals is shown in Table 5-1.
DRDMAADDR[17:0]
DRDMAADDR is used as the source for DRADDR whenever DRDMAEN is
asserted.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Table 5-1 Relationship between DMDMAEN, DRDMACS, and DRIDLE
DRDMAEN
1
1
1
1
DRDMACS
1
0
1
0
DRIDLE
0
0
1
1
ARM DDI0198D
DRCS
1
Unknown
1
0