SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 104

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Caches and Write Buffer
4.4
4-8
TCM and cache access priorities
The priorities that apply to the ARM926EJ-S processor for instruction accesses are
shown in Table 4-5. The ARM926EJ-S processor gives highest priority to an address
that is in the instruction TCM region.
The priorities that apply to the ARM926EJ-S processor for data accesses are shown in
Table 4-6. The Harvard arrangement for the TCM and caches requires that data reads
and writes can access the Instruction TCM for both reads and writes. (The column order
for Table 4-6 is deliberately the same as for instruction accesses in Table 4-5.)
Address in
ITCM Region
Yes
No
No
Yes
Yes
No
No
Copyright © 2001-2003 ARM Limited. All rights reserved.
Address in
ITCM region
Yes
Yes
Yes
No
No
Table 4-5 Instruction access priorities to the TCM and cache
Address in
DTCM region
Yes
Yes
Yes
No
No
No
No
Address in
DTCM region
Yes
No
No
Don't care
Don't care
Table 4-6 Data access priorities to the TCM and cache
Cachable in
page descriptor
Don't care
Cachable
Noncachable
Cachable
Noncachable
Cachable
Noncachable
Cachable in
page descriptor
Don't care
Cachable
Noncachable
Cachable
Noncachable
ARM926EJ-S
behavior
Access DCache
Access DTCM
Access DTCM
Access DTCM
Access ITCM
Access ITCM
Access external memory
ARM926EJ-S
behavior
Access ICache
Access ITCM
Access ITCM
Access ITCM
Access external memory
ARM DDI0198D