SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 46

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.3.5
2.3.6
2-18
Register c4
Fault Status Registers c5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D15
Each two-bit field defines the access permissions for one of the 16 domains (D15-D0)
(see Table 2-14).
Reading from c3 returns the value of the Domain Access Control Register.
Writing to c3 writes the value of the Domain Access Control Register.
You can use the following instructions to access the Domain Access Control Register:
Accessing (reading or writing) this register causes Unpredictable behavior.
Register c5 accesses the Fault Status Registers (FSRs). The FSRs contain the source of
the last instruction or data fault. The instruction-side FSR is intended for debug
purposes only. The FSR is updated for alignment faults, and external aborts that occur
while the MMU is disabled.
D14 D13 D12 D11 D10
Value
00
01
10
11
Copyright © 2001-2003 ARM Limited. All rights reserved.
Meaning
No access
Client
Reserved
Manager
D9
Description
Any access generates a domain fault.
Accesses are checked against the access permission bits in
the section or page descriptor.
Reserved. Currently behaves like the no access mode.
Accesses are not checked against the access permission
bits so a permission fault cannot be generated.
D8
D7
Table 2-14 Domain access control defines
D6
D5
Figure 2-7 Register c3 format
D4
D3
D2
ARM DDI0198D
D1
D0