SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 209

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
Bits
[31:20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12:0]
Function or name
Reserved
Test and clean all
Abort data TLB miss
Abort instruction TLB miss
Disable NC instruction prefetching
Disable block-level clock gating
Disable NCB stores (force NCNB)
MMU disabled, DCache enabled
behavior
Reserved
The reset state of the Debug Override Register is
Bit 13, MMU disabled, DCache enabled behavior
Bit 14, disable NCB stores (force NCNB)
Copyright © 2001-2003 ARM Limited. All rights reserved.
This bit changes the behavior when the MMU is disabled but the DCache
is enabled. During normal operation, if the MMU is disabled, all data
accesses are treated as being NCNB. If Bit 13 is set with the MMU
disabled, and the DCache is enabled, all data accesses are treated as WT.
This behavior can be overridden using the memory region register.
You can use this bit to force all NCB stores to be treated as NCNB stores
at level one. This bit overrides the settings in both the MMU page tables
and the memory region remap register.
Note
Description
Read = Unpredictable
Write = Should Be Zero
0 = Default behavior for test and clean instructions
1 = Modifies the behavior of test and clean, and test, clean, and
invalidate instructions so that they act on the complete cache
0 = Do not abort DTLB miss
1 = Abort DTLB miss
0 = Do not abort ITLB miss
1 = Abort ITLB miss
0 = Enable prefetching
1 = Disable prefetching
0 = Enable block-level clock gating
1 = Disable block-level clock gating
0 = Enable NCB stores
1 = Disable NCB stores (force NCNB)
0 = If MMU disabled. level one access NCNB
1 = If MMU disabled and DCache enabled level one access WT
Read = Unpredictable
Write = Should Be Zero
Table B-1 Debug Override Register
.
CP15 Test and Debug Registers
B-3