SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 155

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
7.1.3
ARM DDI0198D
AHB behavior
This IMB implementation only applies to the ARM926EJ-S processor running code
from a noncachable region of memory. If code is run from a cachable region of memory,
or a different device is used then a different IMB implementation is required. IMBs are
described in Chapter 9 Instruction Memory Barrier.
If instruction prefetching is disabled, all instruction fetches appear on the AHB interface
as single, nonsequential fetches.
If prefetching is enabled then instruction fetches either appear as bursts of four
instructions, or as single, nonsequential fetches. No speculative instruction fetching is
done across a 1KB boundary.
All instruction fetches, including those made in Thumb state, are word transfers (32
bits). In Thumb state a single-word instruction fetch reads two Thumb instructions, and
a four-word burst reads eight instructions.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Noncachable Instruction Fetches
7-3

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