SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 158

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
8.1
8.1.1
8-2
About the ARM926EJ-S external coprocessor interface
Overview
The ARM926EJ-S supports the connection of on-chip coprocessors to the ARM9EJ-S
core through an external coprocessor interface. All types of coprocessor instructions are
supported.
Coprocessors determine the instructions that they have to execute by using a pipeline
follower in the coprocessor. As each instruction arrives from memory it enters both the
ARM9EJ-S pipeline and the coprocessor pipeline. To avoid a critical path for the
instruction being latched by the coprocessor, the coprocessor pipeline must operate one
clock cycle behind the ARM9EJ-S core pipeline.
The two pipelines are synchronized by stalling the ARM9EJ-S core pipeline in its first
Execute cycle whenever an external coprocessor instruction moves from the Decode to
the Execute stage.
To enable coprocessors to continue execution of coprocessor data operations while the
ARM9EJ-S core pipeline is stalled (for example, while waiting for a cache linefill to
occur), the coprocessor receives the clock CLK, and a clock enable signal CPCLKEN.
You can use these to produce a gated coprocessor clock with the circuit shown in
Figure 8-1.
Figure 8-2 indicates the timing for these signals and when the coprocessor pipeline
must advance its state.
Copyright © 2001-2003 ARM Limited. All rights reserved.
CLK
CPCLKEN
Coproc clock
Figure 8-1 Producing a coprocessor clock
CPCLKEN
Figure 8-2 Coprocessor clocking
CLK
ARM DDI0198D
Coproc clock