SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 235

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Fully-associative cache
Half-rate clocking (ETM)
Halfword
Halt mode
High vectors
Host
ICache
IGN
Ignore (IGN)
Illegal instruction
IMB
Implementation-defined
Implementation-specific
ARM DDI0198D
A cache that has just one cache set that consists of the entire cache. The number of cache
entries is the same as the number of cache ways.
See also Direct-mapped cache.
Dividing the trace clock by two so that the TPA can sample trace data signals on both
the rising and falling edges of the trace clock. The primary purpose of half-rate clocking
is to reduce the signal transition rate on the trace clock of an ASIC for very high-speed
systems.
A 16-bit data item.
One of two mutually exclusive debug modes. In halt mode all processor execution halts
when a breakpoint or watchpoint is encountered. All processor state, coprocessor state,
memory and input/output locations can be examined and altered by the JTAG interface.
See also Monitor debug-mode.
Alternative locations for exception vectors. The high vector address range is near the
top of the address space, rather than at the bottom.
A computer that provides data and other services to another computer. Especially, a
computer providing debugging services to a target being debugged.
A block of on-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used instructions. This is
done to greatly reduce the average speed of memory accesses and so to increase
processor performance.
See Ignore.
Must ignore memory writes.
An instruction that is architecturally Undefined.
See Instruction Memory Barrier.
Means that the behavior is not architecturally defined, but should be defined and
documented by individual implementations.
Means that the behavior is not architecturally defined, and does not have to be
documented by individual implementations. Used when there are a number of
implementation options available and the option chosen does not affect software
compatibility.
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