SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 50

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2-22
Function/operation
Invalidate ICache and DCache
Invalidate ICache
Invalidate ICache single entry (MVA)
Invalidate ICache single entry (Set/Way)
Prefetch ICache line (MVA)
Invalidate DCache
Invalidate DCache single entry (MVA)
Table 2-18 lists the cache operation functions and the associated data and instruction
formats for c7.
Function
Prefetch ICache line
Drain write buffer
Wait for interrupt
Copyright © 2001-2003 ARM Limited. All rights reserved.
Table 2-17 Function descriptions register c7 (continued)
Description
Performs an ICache lookup of the specified modified
virtual address. If the cache misses, and the region is
cachable, a linefill is performed.
This instruction acts as an explicit memory barrier. It drains
the contents of the write buffers of all memory stores
occurring in program order before this instruction is
completed. No instructions occurring in program order
after this instruction are executed until it completes. This
can be used when timing of specific stores to the level two
memory system has to be controlled (for example, when a
store to an interrupt acknowledge location has to complete
before interrupts are enabled).
This instruction drains the contents of the write buffers,
puts the processor into a low-power state, and stops it from
executing further instructions until an interrupt (or debug
request) occurs. When an interrupt does occur, the MCR
instruction completes and the IRQ or FIQ handler is entered
as normal. The return link in R14_irq or R14_fiq contains
the address of the MCR instruction plus eight, so that the
typical instruction used for interrupt return (
) returns to the instruction following the MCR.
Data format
SBZ
SBZ
MVA
Set/Way
MVA
SBZ
MVA
Table 2-18 Cache operations c7
Instruction
ARM DDI0198D