SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 995

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

44. Image Sensor Interface (ISI)
44.1
Figure 44-1. ISI Connection Example
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
Description
The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and
provides image capture in various formats. It does data conversion, if necessary, before the stor-
age in memory through DMA.
The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of
functionalities.
In grayscale mode, the data stream is stored in memory without any processing and so is not
compatible with the LCD controller.
Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB
output on the preview path is compatible with the LCD controller. This module outputs the data
in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD
display resolution (See
Several input formats such as preprocessed RGB or YCbCr are supported through the data bus
interface.
It supports two modes of synchronization:
Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used).
The polarity of the synchronization pulse is programmable to comply with the sensor signals.
Table 44-1.
Signal
ISI_VSYNC
ISI_HSYNC
ISI_DATA[11..0]
ISI_MCK
ISI_PCK
1. The hardware with ISI_VSYNC and ISI_HSYNC signals
2. The International Telecommunication Union Recommendation ITU-R BT.656-4 Start-of-
Active-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence.
Image Sensor
data[11..0]
I/O Description
HSYNC
VSYNC
PCLK
CLK
Table 44-3 on page
OUT
Dir
IN
IN
IN
IN
Description
Vertical Synchronization
Horizontal Synchronization
Sensor Pixel Data
Master Clock Provided to the Image Sensor
Pixel Clock Provided by the Image Sensor
999).
ISI_DATA[11..0]
ISI_MCK
ISI_PCK
ISI_VSYNC
ISI_HSYNC
Image Sensor Interface
SAM9G25
SAM9G25
995
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