SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 1109

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 46-4. SMC Timings - NRD Controlled Read and NWE Controlled Write
46.15 DDRSDRC Timings
46.16 Peripheral Timings
46.16.1
46.16.1.1
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
Master Write Mode
Master Read Mode
A0/A1/NBS[3:0]
D0 - D31
/A2-A25
NWE
NCS
NRD
SPI
Maximum SPI Frequency
SMC6
SMC5
NRD Controlled READ
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR
modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
The following formulas give maximum SPI frequency in Master read and write modes and in
Slave read and write modes.
with NO HOLD
SMC7
• DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
• LP-DDR limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK)
• SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
• SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
• LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)
The SPI is only sending data to a slave device such as an LCD, for example. The limit is
given by SPI
speed (see
T
DataFlash (AT45DB642D), T
This gives, F
f
SPCK
valid
SMC1
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI
Max
SMC2
=
SMC17
Section 46.10
SMC18
2
SPCK
NWE Controlled WRITE
--------------------------------------------------------
SPI
(or SPI
with NO HOLD
Max = 39 MHz @ VDDIO = 3.3V.
0
SMC16
orSPI
SMC15
5
) timing. Since it gives a maximum frequency above the maximum pad
1
SMC21
SMC21
3
SMC21
“I/Os”), the max SPI frequency is the one from the pad.
+
SMC6
valid
T
SMC5
valid
(orT
NRD Controlled READ
v
SMC7
) is 12 ns Max.
with HOLD
SMC3
SMC4
SMC17
SMC18
NWE Controlled WRITE
with HOLD
SMC16
SMC15
SAM9G25
SAM9G25
SMC19
SMC20
SMC19
1109
1109