SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 812

• Manufacturer Part Number: SAM9G25
• Manufacturer: Atmel Corporation

Specifications of SAM9G25

• Flash (kbytes): 0 Kbytes
• Pin Count: 247
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 7
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

39.6
39.6.1
39.6.2
812
812
Product Dependencies
SAM9G25
SAM9G25
I/O Lines
Power Management
The pins used for interfacing the USART may be multiplexed with the PIO lines. The program-
mer must first program the PIO controller to assign the desired USART pins to their peripheral
function. If I/O lines of the USART are not used by the application, they can be used for other
purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also
be enabled.
Table 39-3.
The USART is not continuously clocked. The programmer must first enable the USART Clock in
the Power Management Controller (PMC) before using the USART. However, if the application
does not require USART operations, the USART clock can be stopped when not needed and be
restarted later. In this case, the USART will resume its operations where it left off.
Configuring the USART does not require the USART clock to be enabled.
Instance
USART0
USART0
USART0
USART0
USART0
USART1
USART1
USART1
USART1
USART1
USART2
USART2
USART2
USART2
USART2
USART3
USART3
USART3
USART3
USART3
I/O Lines
Signal
RXD0
SCK0
RXD1
RXD2
SCK2
RXD3
CTS0
RTS0
TXD0
CTS1
RTS1
SCK1
TXD1
CTS2
RTS2
TXD2
CTS3
RTS3
SCK3
TXD3
I/O Line
PC23
PC28
PC27
PC29
PC25
PC24
PC26
PC22
PB1
PB0
PB2
PA3
PA2
PA1
PA4
PA0
PA6
PA5
PA8
PA7
11032A–ATARM–27-Jul-11
11032A–ATARM–27-Jul-11
Peripheral
C
C
C
A
A
A
A
A
A
A
B
B
A
B
A
B
B
B
B
B